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ADP3801AR PDF预览

ADP3801AR

更新时间: 2024-02-10 17:02:36
品牌 Logo 应用领域
亚德诺 - ADI 电池开关
页数 文件大小 规格书
20页 258K
描述
High Frequency Switch Mode Dual Li-Ion Battery Chargers

ADP3801AR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:16
Reach Compliance Code:unknown风险等级:5.72
模拟集成电路 - 其他类型:BATTERY CHARGE CONTROLLER控制模式:CURRENT/VOLTAGE-MODE
控制技术:PULSE WIDTH MODULATION最大输入电压:20 V
最小输入电压:4.1 V标称输入电压:10 V
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm湿度敏感等级:NOT SPECIFIED
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
标称输出电压:3.3 V封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):220
认证状态:COMMERCIAL座面最大高度:1.75 mm
表面贴装:YES切换器配置:SINGLE
最大切换频率:250 kHz温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

ADP3801AR 数据手册

 浏览型号ADP3801AR的Datasheet PDF文件第14页浏览型号ADP3801AR的Datasheet PDF文件第15页浏览型号ADP3801AR的Datasheet PDF文件第16页浏览型号ADP3801AR的Datasheet PDF文件第17页浏览型号ADP3801AR的Datasheet PDF文件第18页浏览型号ADP3801AR的Datasheet PDF文件第20页 
ADP3801/ADP3802  
Board Layout Suggestions  
4) Connect the positive side of CIN as close as possible to the  
source of the P-channel MOSFET (or the emitter of the  
PNP). This capacitor provides the ac current to the pass  
transistor.  
When laying out the printed circuit board, the following check-  
list should be used to ensure proper operation of the ADP3801  
and ADP3802. These items are also illustrated graphically in  
the layout diagram on the evaluation board application note.  
Check the following in your layout:  
5) Connect the input decoupling capacitor (0.l µF) close to the  
VCC input of the IC. This capacitor carries the DRV peak  
currents.  
1) The IC ground must return to a) the power and b) the signal  
grounds with as short of leads as possible. If a double layer  
PCB board is used and a ground plane is available, connect  
all grounded parts directly to the ground plane. The ground  
returns to the anode of the Schottky diode and the minus  
terminal of CIN should have as short of lead lengths as possible.  
6) Connect the 0.1 µF LDO decoupling capacitor as close as  
possible to the VL pin.  
7) The RESET pin has an internal pull-up, and should be pulled  
low with an external resistor. The RESET pin is high imped-  
ance and should not be allowed to float.  
2) Connect the IC’s current sense pins (CS+ and CS–) to RCS  
with as short of leads (<0.5 inch) as possible.  
3) Route the CS+ and CS– traces together with minimum spac-  
ing. The filter capacitors should be close to the IC.  
REV. 0  
–19–  

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