Datasheet > ADP3650JCPZ-RL

ADP3650JCPZ-RL

更新时间： 2024-09-25 14:49:55

品牌	Logo	应用领域
亚德诺 - ADI		驱动光电二极管接口集成电路驱动器
页数	文件大小	规格书
13页	421K
描述
Dual, Bootstrapped, 12 V MOSFET Driver with Output Disable

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ADP3650JCPZ-RL 数据手册

Dual, Bootstrapped, 12 V MOSFET

Driver with Output Disable

Data Sheet

ADP3650

FEATURES

GENERAL DESCRIPTION

All-in-one synchronous buck driver

Bootstrapped high-side drive

One PWM signal generates both drives

Anti-crossconduction protection circuitry

OD for disabling the driver outputs

The ADP3650 is a dual, high voltage MOSFET driver optimized

for driving two N-channel MOSFETs, the two switches in a

nonisolated synchronous buck power converter. Each driver is

capable of driving a 3000 pF load with a 45 ns propagation delay

and a 25 ns transition time. One of the drivers can be boot-

strapped and is designed to handle the high voltage slew rate

associated with floating high-side gate drivers. The ADP3650

includes overlapping drive protection to prevent shoot-through

current in the external MOSFETs.

APPLICATIONS

Telecom and datacom networking

Industrial and medical systems

Point of load conversion: memory, DSP, FPGA, ASIC

The

pin shuts off both the high-side and the low-side

MOSFETs to prevent rapid output capacitor discharge during

system shutdown.

The ADP3650 is specified over the temperature range of −40°C

to +85°C and is available in 8-lead SOIC_N and 8-lead LFCSP

packages.

FUNCTIONAL BLOCK DIAGRAM

12V

VCC

BST

ADP3650

BST2

LATCH

BST1

DRVH

DELAY

BST

INDUCTOR

CMP

VCC

CMP

DRVL

PGND

CONTROL

LOGIC

DELAY

Figure 1.

Rev. B

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rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

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