Datasheet > ADP3650JRZ

ADP3650JRZ

更新时间： 2024-01-11 11:21:04

品牌	Logo	应用领域
亚德诺 - ADI		驱动光电二极管接口集成电路驱动器
页数	文件大小	规格书
12页	374K
描述
Dual, Bootstrapped, 12 V MOSFET Driver with Output Disable

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ADP3650JRZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	SOIC-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.78
Samacsys Description：	MOSFET Driver High/Low Side Inv/Non-Inv	高边驱动器：	YES
接口集成电路类型：	AND GATE BASED MOSFET DRIVER	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	1	功能数量：	1
端子数量：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	12 V
认证状态：	Not Qualified	座面最大高度：	1.75 mm
子类别：	MOSFET Drivers	最大供电电压：	13.2 V
最小供电电压：	4.15 V	标称供电电压：	12 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	断开时间：	0.035 µs
接通时间：	0.07 µs	宽度：	3.9 mm
Base Number Matches：	1

ADP3650JRZ 数据手册

Dual, Bootstrapped, 12 V MOSFET

Driver with Output Disable

Data Sheet

ADP3650

FEATURES

GENERAL DESCRIPTION

All-in-one synchronous buck driver

Bootstrapped high-side drive

One PWM signal generates both drives

Anti-crossconduction protection circuitry

OD for disabling the driver outputs

The ADP3650 is a dual, high voltage MOSFET driver optimized

for driving two N-channel MOSFETs, the two switches in a

nonisolated synchronous buck power converter. Each driver is

capable of driving a 3000 pF load with a 45 ns propagation delay

and a 25 ns transition time. One of the drivers can be boot-

strapped and is designed to handle the high voltage slew rate

associated with floating high-side gate drivers. The ADP3650

includes overlapping drive protection to prevent shoot-through

current in the external MOSFETs.

APPLICATIONS

Telecom and datacom networking

Industrial and medical systems

Point of load conversion: memory, DSP, FPGA, ASIC

The

pin shuts off both the high-side and the low-side

MOSFETs to prevent rapid output capacitor discharge during

system shutdown.

The ADP3650 is specified over the temperature range of −40°C

to +85°C and is available in 8-lead SOIC_N and 8-lead LFCSP

packages.

FUNCTIONAL BLOCK DIAGRAM

12V

VCC

BST

ADP3650

BST2

LATCH

BST1

DRVH

DELAY

BST

INDUCTOR

CMP

VCC

CMP

DRVL

PGND

CONTROL

LOGIC

DELAY

Figure 1.

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

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