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ADP3421JRU-REEL7 PDF预览

ADP3421JRU-REEL7

更新时间: 2024-02-11 10:11:03
品牌 Logo 应用领域
安森美 - ONSEMI 开关光电二极管
页数 文件大小 规格书
13页 143K
描述
SWITCHING CONTROLLER, PDSO28, TSSOP-28

ADP3421JRU-REEL7 技术参数

生命周期:Active零件包装代码:SSOP
包装说明:TSSOP,针数:28
Reach Compliance Code:unknown风险等级:5.34
模拟集成电路 - 其他类型:SWITCHING CONTROLLER最大输入电压:5 V
最小输入电压:3 V标称输入电压:3.3 V
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:9.7 mm湿度敏感等级:3
功能数量:1端子数量:28
最高工作温度:100 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240认证状态:COMMERCIAL
座面最大高度:1.2 mm表面贴装:YES
切换器配置:SINGLE温度等级:OTHER
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm

ADP3421JRU-REEL7 数据手册

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ADP3421  
Pin  
Mnemonic  
Function  
15  
16  
SD  
Shutdown Input. When this pin is pulled low, the IC shuts down and all regulation functions will be disabled.  
PWRGD  
Power-Good Output. This signal will go high only when the SD pin is high to allow IC operation, the UVLO  
and VCC pins are above their respective start-up thresholds, the SSC and SSL pins are above a voltage where  
soft start is completed, and the voltage at the CORE pin is within the specified limits of the programmed VID  
voltage. By choosing the soft-start capacitor for the core larger than that for the linear regulators, at start-up  
the core and linear outputs should all be in regulation before PWRGD is asserted.  
17  
UVLO  
Undervoltage Lockout Input. This pin monitors the input voltage through a resistor divider. When the pin  
voltage is below a specified threshold, the IC enters into UVLO mode regardless of the status of SD. When  
in UVLO mode, a current source is switched on at this pin, which sinks current from the external resistor  
divider. The generated UVLO hysteresis is equal to the current sink value times the upper divider resistor.  
18  
19  
SSL  
SSC  
Linear Regulator Soft Start. During power-up, an external soft-start capacitor is charged by a current source  
to control the ramp-up rates of the linear regulators.  
Core Voltage Soft Start. During power-up, an external soft-start capacitor is charged by a current source to  
control the ramp-up rate of the core voltage.  
20  
21  
CORE  
Core Converter Voltage Monitor. This pin is used to monitor the core voltage for power-good verification.  
DACOUT  
VID-programmed Digital-to-Analog Converter Output. This voltage is the reference voltage for output  
voltage regulation.  
22  
23  
GND  
OUT  
Ground.  
Logic-Level Drive Signal Output of Core Controller. This pin provides the drive command signal to the IN  
pin of the ADP3410 driver. This pin is not capable of directly driving a power MOSFET.  
24  
25  
VCC  
RAMP  
Power Supply.  
Current Ramp Input. This pin provides the negative feedback for the core output voltage. The switched sink/  
source current from this pin, which is set up at the VHYS pin, works against the terminating resistance at this  
pin to set the hysteresis for the hysteretic control.  
26  
REG  
Regulation Voltage Summing Input. In the recommended configuration, the DACOUT voltage and the core  
voltage are summed at this pin to establish regulation with output voltage positioning.  
27  
28  
CS+  
CS–  
Current Limit Positive Sense. This pin senses the positive node of the current sense resistor.  
Current Limit Negative Sense. This pin connects through a resistor to the negative node of the current sense  
resistor. A current flows out of the pin, as programmed at the CLSET pin. When this pin is more negative  
than the CS+ pin, the current limit comparator is triggered and the current flowing out of the pin is reduced  
to two-thirds of its previous value, producing a current limit hysteresis.  
REV. 0  
–5–  

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