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ADP3335ARM-5-REEL7 PDF预览

ADP3335ARM-5-REEL7

更新时间: 2024-02-27 05:27:50
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 光电二极管输出元件调节器
页数 文件大小 规格书
17页 1274K
描述
5 V FIXED POSITIVE LDO REGULATOR, 0.37 V DROPOUT, PDSO8, MO-187AA, MSOP-8

ADP3335ARM-5-REEL7 技术参数

是否无铅: 含铅生命周期:Active
零件包装代码:TSSOP包装说明:MSOP-8
针数:8Reach Compliance Code:unknown
风险等级:5.17可调性:FIXED
最大回动电压 1:0.37 V标称回动电压 1:0.2 V
最大绝对输入电压:16 V最大输入电压:12 V
最小输入电压:2.6 VJESD-30 代码:S-PDSO-G8
长度:3 mm功能数量:1
输出次数:1端子数量:8
工作温度TJ-Max:150 °C工作温度TJ-Min:-40 °C
最高工作温度:85 °C最低工作温度:-40 °C
最大输出电流 1:0.5 A最大输出电压 1:5.115 V
最小输出电压 1:4.885 V标称输出电压 1:5 V
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
调节器类型:FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR座面最大高度:1.1 mm
表面贴装:YES技术:BIPOLAR
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL最大电压容差:2.3%
宽度:3 mmBase Number Matches:1

ADP3335ARM-5-REEL7 数据手册

 浏览型号ADP3335ARM-5-REEL7的Datasheet PDF文件第9页浏览型号ADP3335ARM-5-REEL7的Datasheet PDF文件第10页浏览型号ADP3335ARM-5-REEL7的Datasheet PDF文件第11页浏览型号ADP3335ARM-5-REEL7的Datasheet PDF文件第13页浏览型号ADP3335ARM-5-REEL7的Datasheet PDF文件第14页浏览型号ADP3335ARM-5-REEL7的Datasheet PDF文件第15页 
ADP3335  
2. The thermal pad of the LFCSP package provides a low  
PRINTED CIRCUIT BOARD LAYOUT  
CONSIDERATIONS  
thermal impedance path (approximately 20°C/W) to the  
PCB. Therefore, the PCB must be properly designed to  
effectively conduct heat away from the package. This is  
achieved by adding thermal vias to the PCB, which provide  
a thermal path to the inner or bottom layers. See Figure 25  
for the recommended via pattern. Note that the via  
diameter is small to prevent the solder from flowing  
through the via and leaving voids in the thermal pad solder  
joint.  
All surface-mount packages rely on the traces of the PC board  
to conduct heat away from the package. Use the following  
general guidelines when designing printed circuit boards to  
improve both electrical and thermal performance.  
1. Keep the output capacitor as close as possible to the output  
and ground pins.  
2. Keep the input capacitor as close as possible to the input  
and ground pins.  
Also, note that the thermal pad is attached to the die  
substrate, so the thermal planes to which the thermal vias  
connect must be electrically isolated or tied to VIN. Do  
NOT connect the thermal pad to ground.  
3. PC board traces with larger cross sectional areas will  
remove more heat from the ADP3335. For optimum heat  
transfer, specify thick copper and use wide traces.  
3. The solder mask opening should be about 120 µ (4.7 mils)  
larger than the pad size, resulting in a minimum 60 µm  
(2.4 mils) clearance between the pad and the solder mask.  
4. It is not recommended to use solder mask or silkscreen on  
the PCB traces adjacent to the ADP3335s pins, since doing  
so will increase the junction-to-ambient thermal resistance  
of the package.  
4. The paste mask opening is typically designed to match the  
pad size used on the peripheral pads of the LFCSP package.  
This should provide a reliable solder joint as long as the  
stencil thickness is about 0.125 mm. The paste mask for the  
thermal pad needs to be designed for the maximum  
5. Use additional copper layers or planes to reduce the  
thermal resistance. When connecting to other layers, use  
multiple vias, if possible.  
coverage to effectively remove the heat from the package.  
However, due to the presence of thermal vias and the size  
of the thermal pad, eliminating voids may not be possible.  
LFCSP LAYOUT CONSIDERATIONS  
The LFCSP package has an exposed die paddle on the bottom,  
which efficiently conducts heat to the PCB. In order to achieve  
the optimum performance from the LFCSP package, special  
consideration must be given to the layout of the PCB. Use the  
following layout guidelines for the LFCSP package.  
5. The recommended paste mask stencil thickness is  
0.125 mm. A laser cut stainless steel stencil with  
trapezoidal walls should be used. A “No Clean” Type 3  
solder paste should be used for mounting the LFCSP  
package. Also, a nitrogen purge during the reflow process is  
recommended.  
2× VIAS, 0.250∅  
35µm PLATING  
0.73  
0.30  
6. The package manufacturer recommends that the reflow  
temperature should not exceed 220°C and the time above  
liquidus is less than 75 seconds. The preheat ramp should  
be 3°C/second or lower. The actual temperature profile  
depends on the board density and must be determined by  
the assembly house as to what works best.  
1.80  
0.90  
2.36  
0.50  
1.40  
1.90  
SHUTDOWN MODE  
3.36  
SD  
Applying a TTL high signal to the shutdown ( ) pin or tying it  
Figure 25. 3 mm × 3 mm LFCSP Pad Pattern  
(Dimensions shown in millimeters)  
SD  
to the input pin, turns the output ON. Pulling  
down to 0.4 V  
or below, or tying it to ground, turns the output OFF. In shut-  
down mode, quiescent current is reduced to a typical value of  
10 nA.  
1. The pad pattern is given in Figure 25. The pad dimension  
should be followed closely for reliable solder joints, while  
maintaining reasonable clearances to prevent solder  
bridging.  
Rev. A | Page 11 of 16  
 
 

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