Datasheet > 驱动程序和接口 > MOSFET 驱动器> ADP3120JRZ

ADP3120JRZ

更新时间： 2024-02-07 06:36:44

品牌	Logo	应用领域
亚德诺 - ADI		驱动器 MOSFET驱动器驱动程序和接口接口集成电路光电二极管
页数	文件大小	规格书
16页	275K
描述
Dual Bootstrapped 12 V MOSFET Driver with Output Disable

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ADP3120JRZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	LEAD FREE, MS-012AA, SOIC-8	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.72
Is Samacsys：	N	高边驱动器：	YES
接口集成电路类型：	HALF BRIDGE BASED MOSFET DRIVER	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
功能数量：	2	端子数量：	8
最高工作温度：	85 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP8,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	12 V	认证状态：	Not Qualified
座面最大高度：	1.75 mm	子类别：	MOSFET Drivers
最大供电电压：	13.2 V	最小供电电压：	4.15 V
标称供电电压：	12 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
断开时间：	0.045 µs	接通时间：	0.07 µs
宽度：	3.9 mm	Base Number Matches：	1

ADP3120JRZ 数据手册

ADP3120

THEORY OF OPERATION

The ADP3120 is optimized for driving two N-channel

MOSFETs in a synchronous buck converter topology. A single

PWM input signal is all that is required to properly drive the

high-side and the low-side MOSFETs. Each driver is capable of

driving a 3 nF load at speeds up to 500 kHz.

OVERLAP PROTECTION CIRCUIT

The overlap protection circuit prevents both of the main power

switches, Q1 and Q2, from being on at the same time. This is

done to prevent shoot-through currents from flowing through

both power switches and the associated losses that can occur

during their on/off transitions. The overlap protection circuit

accomplishes this by adaptively controlling the delay from the

Q1 turn off to the Q2 turn on, and by internally setting the

delay from the Q2 turn off to the Q1 turn on.

A more detailed description of the ADP3120 and its features

follows. See Figure 1.

LOW-SIDE DRIVER

The low-side driver is designed to drive a ground-referenced

N-channel MOSFET. The bias to the low-side driver is

internally connected to the VCC supply and PGND.

To prevent the overlap of the gate drives during the Q1 turn off

and the Q2 turn on, the overlap circuit monitors the voltage at

the SW pin. When the PWM input signal goes low, Q1 begins

to turn off (after propagation delay). Before Q2 can turn on, the

overlap protection circuit makes sure that SW has first gone

high and then waits for the voltage at the SW pin to fall from

When the driver is enabled, the driver’s output is 180° out of

phase with the PWM input. When the ADP3120 is disabled,

the low-side gate is held low.

V_INto 1 V. Once the voltage on the SW pin falls to 1 V, Q2

begins turn on. If the SW pin has not gone high first, the Q2

turn on is delayed by a fixed 150 ns. By waiting for the voltage

on the SW pin to reach 1 V or for the fixed delay time, the

overlap protection circuit ensures that Q1 is off before Q2 turns

on, regardless of variations in temperature, supply voltage, input

pulse width, gate charge, and drive current. If SW does not go

below 1 V after 190 ns, DRVL turns on. This can occur if the

current flowing in the output inductor is negative and is flowing

through the high-side MOSFET body diode.

HIGH-SIDE DRIVER

The high-side driver is designed to drive a floating N-channel

MOSFET. The bias voltage for the high-side driver is developed

by an external bootstrap supply circuit, which is connected

between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap

capacitor, C_BST1. C_BST2and R_BSTare included to reduce the high-

side gate drive voltage and to limit the switch node slew rate

(called a Boot-Snap circuit—see the Application Information

section for more details). When the ADP3120 starts up, the SW

pin is at ground, so the bootstrap capacitor charges up to VCC

through D1. When the PWM input goes high, the high-side

driver begins to turn on the high-side MOSFET, Q1, by pulling

charge out of C_BST1and C_BST2. As Q1 turns on, the SW pin rises

up to V_IN, forcing the BST pin to V_IN+ V_C(BST), which is enough

gate-to-source voltage to hold Q1 on. To complete the cycle, Q1

is switched off by pulling the gate down to the voltage at the SW

pin. When the low-side MOSFET, Q2, turns on, the SW pin is

pulled to ground. This allows the bootstrap capacitor to charge

up to VCC again.

The output of the high-side driver is in phase with the PWM

input. When the driver is disabled, the high-side gate is held low.

Rev. 0 | Page 9 of 16

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与ADP3120JRZ相关器件

型号	品牌	获取价格	描述	数据表
ADP3120JRZ-RL	ADI	获取价格	Dual Bootstrapped 12 V MOSFET Driver with Output Disable
ADP3121	ONSEMI	获取价格	Dual Bootstrapped, 12 V MOSFET Driver with Output Disable
ADP3121JCPZ-RL	ONSEMI	获取价格	Dual Bootstrapped, 12 V MOSFET Driver with Output Disable
ADP3121JRZ-RL	ONSEMI	获取价格	Dual Bootstrapped, 12 V MOSFET Driver with Output Disable
ADP3152	ADI	获取价格	5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor
ADP3152AR	ADI	获取价格	5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor
ADP3152AR-REEL	ADI	获取价格	IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, PDSO16, SOIC-16, Switching Regulator
ADP3153	ADI	获取价格	5-Bit Programmable Dual Power Supply Controller for Pentium II Processor
ADP3153ARU	ADI	获取价格	5-Bit Programmable Dual Power Supply Controller for Pentium II Processor
ADP3153ARU-REEL	ADI	获取价格	IC SWITCHING CONTROLLER, 250 kHz SWITCHING FREQ-MAX, PDSO20, TSSOP-20, Switching Regulator

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