ADP1740ACPZ-1.2-R7

更新时间： 2024-02-09 23:24:20

品牌	Logo	应用领域
亚德诺 - ADI		稳压器
页数	文件大小	规格书
20页	743K
描述
2 A, Low VIN, Low Dropout Linear Regulator

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ADP1740ACPZ-1.2-R7 数据手册

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ADP1740/ADP1741

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

12 VOUT

11 VOUT

10 VOUT

12 VOUT

11 VOUT

10 VOUT

VIN

ADP1740

TOP VIEW

(Not to Scale)

ADP1741

TOP VIEW

(Not to Scale)

SENSE

9 ADJ

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES

THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND

INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD

BE CONNECTED TO THE GROUND PLANE ON THE BOARD.

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES

THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND

INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD

BE CONNECTED TO THE GROUND PLANE ON THE BOARD.

Figure 3. ADP1740 Pin Configuration

Figure 4. ADP1741 Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

ADP1740

ADP1741

Mnemonic

Description

1, 2, 3, 15, 16 1, 2, 3, 15, 16 VIN

Regulator Input Supply. Bypass VIN to GND with a 4.7 µF or greater capacitor. Note that all

five VIN pins must be connected to the source supply.

Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For

automatic startup, connect EN to VIN.

Power-Good Output. This open-drain output requires an external pull-up resistor to VIN. If

the part is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below

90% of the nominal output voltage, the PG pin immediately transitions low.

GND

Ground.

Soft Start Pin. A capacitor connected to this pin determines the soft start time.

Not Connected. No internal connection.

Sense Input. This pin measures the actual output voltage at the load and feeds it to the error

amplifier. Connect the SENSE pin as close to the load as possible to minimize the effect of IR

drop between the regulator output and the load.

SENSE

ADJ

Adjust Pin. A resistor divider from VOUT to ADJ sets the output voltage.

10, 11, 12,

13, 14

10, 11, 12,

13, 14

VOUT

Regulated Output Voltage. Bypass VOUT to GND with a 4.7 µF or greater capacitor. Note that

all five VOUT pins must be connected to the load.

Exposed

pad

The exposed pad on the bottom of the LFCSP enhances thermal performance and is

electrically connected to GND inside the package. It is recommended that the exposed pad

be connected to the ground plane on the board.

Rev. E | Page 6 of 20

1...3 4 567 8 9...20

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