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ADP1711AUJZ-0.95R7 PDF预览

ADP1711AUJZ-0.95R7

更新时间： 2024-01-03 21:36:14
品牌 Logo 应用领域
亚德诺 - ADI 稳压器
页数 文件大小 规格书
16页 422K
描述
150 mA, Low Dropout, CMOS Linear Regulator

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ADP1711AUJZ-0.95R7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSOT
包装说明：VSSOP, TSOP5/6,.11,37针数：5
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：7.87
可调性：FIXED最大回动电压 1：0.3 V
标称回动电压 1：0.18 V最大绝对输入电压：6 V
最大输入电压：5.5 V最小输入电压：2.5 V
JESD-30 代码：R-PDSO-G5JESD-609代码：e3
长度：2.9 mm最大电网调整率：0.0039%
最大负载调整率：0.0053%湿度敏感等级：1
功能数量：1输出次数：1
端子数量：5工作温度TJ-Max：125 °C
工作温度TJ-Min：-40 °C最大输出电流 1：0.15 A
最大输出电压 1：0.969 V最小输出电压 1：0.931 V
标称输出电压 1：0.95 V封装主体材料：PLASTIC/EPOXY
封装代码：VSSOP封装等效代码：TSOP5/6,.11,37
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
调节器类型：FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR座面最大高度：1 mm
子类别：Other Regulators表面贴装：YES
技术：CMOS端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.95 mm
端子位置：DUAL处于峰值回流温度下的最长时间：40
最大电压容差：2%宽度：1.6 mm
Base Number Matches：1

ADP1711AUJZ-0.95R7 数据手册

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ADP1710/ADP1711  
THEORY OF OPERATION  
The ADP1710/ADP1711 are low dropout, CMOS linear  
regulators that use an advanced, proprietary architecture to  
provide high power supply rejection ratio (PSRR) and excellent  
line and load transient response with just a small 1 μF ceramic  
output capacitor. Both devices operate from a 2.5 V to 5.5 V  
input rail and provide up to 150 mA of output current.  
Incorporating a novel scaling architecture, ground current is  
very low when driving light loads. Ground current in shutdown  
mode is typically 100 nA.  
ADJUSTABLE OUTPUT VOLTAGE  
(ADP1710 ADJUSTABLE)  
The ADP1710 adjustable version can have its output voltage  
set over a 0.8 V to 5.0 V range. The output voltage is set by  
connecting a resistive voltage divider from OUT to ADJ. The  
output voltage is calculated using the equation  
V
OUT = 0.8 V (1 + R1/R2)  
(1)  
where:  
R1 is the resistor from OUT to ADJ.  
R2 is the resistor from ADJ to GND.  
IN  
OUT  
The maximum bias current into ADJ is 100 nA, so for less  
than 0.5% error due to the bias current, use values less than  
60 kΩ for R2.  
CURRENT LIMIT  
THERMAL PROTECT  
+
BYPASS CAPACITOR (ADP1711)  
SHUTDOWN  
AND UVLO  
The ADP1711 allows for an external bypass capacitor to be  
connected to the internal reference, which reduces output  
voltage noise and improves power supply rejection. A low  
leakage capacitor of 1 nF or greater (10 nF is recommended)  
must be connected between the BYP and GND pins.  
NC/  
ADJ/  
BYP  
EN  
REFERENCE  
GND  
NC = NO CONNECT  
Figure 18. Internal Block Diagram  
ENABLE FEATURE  
Internally, the ADP1710/ADP1711 each consist of a reference,  
an error amplifier, a feedback voltage divider, and a PMOS pass  
transistor. Output current is delivered via the PMOS pass  
device, which is controlled by the error amplifier. The error  
amplifier compares the reference voltage with the feedback  
voltage from the output and amplifies the difference. If the  
feedback voltage is lower than the reference voltage, the gate of  
the PMOS device is pulled lower, allowing more current to pass  
and increasing the output voltage. If the feedback voltage is  
higher than the reference voltage, the gate of the PMOS device  
is pulled higher, allowing less current to pass and decreasing the  
output voltage.  
The ADP1710/ADP1711 use the EN pin to enable and disable  
the OUT pin under normal operating conditions. As shown in  
Figure 19, when a rising voltage on EN crosses the active  
threshold, OUT turns on. When a falling voltage on EN crosses  
the inactive threshold, OUT turns off.  
EN  
The ADP1710 is available in two versions, one with fixed output  
voltage options and one with an adjustable output voltage. The  
fixed output voltage option is set internally to one of sixteen  
values between 0.75 V and 3.3 V, using an internal feedback  
network. The adjustable output voltage can be set to between 0.8  
V and 5.0 V by an external voltage divider connected from OUT  
to ADJ. The ADP1711 is available with fixed output voltage  
options and features a bypass pin, which allows an external  
capacitor to be connected, which reduces internal reference  
noise. All devices are controlled by an enable pin (EN).  
2
OUT  
V
V
= 5V  
IN  
= 1.6V  
= 1µF  
OUT  
C
C
IN  
= 1µF  
= 10mA  
OUT  
LOAD  
I
TIME (1ms/DIV)  
Figure 19. ADP1710 Adjustable Typical EN Pin Operation  
Rev. 0 | Page 8 of 16  
 
 
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