Datasheet > ADP161

ADP161

更新时间： 2022-05-13 19:04:49

品牌	Logo	应用领域
亚德诺 - ADI		稳压器
页数	文件大小	规格书
20页	513K
描述
Ultralow Quiescent Current, 150 mA, CMOS Linear Regulator

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ADP161 数据手册

ADP160/ADP161

SPECIFICATIONS

V_IN= (V_OUT+ 0.5 V) or 2.2 V, whichever is greater; EN = V_IN, I_OUT= 10 mA, C_IN= C_OUT= 1 μF, T_A= 25°C, unless otherwise noted.

Table 1.

Parameter

Symbol

V_IN

Conditions

Min Typ

2.2

Max

Unit

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

T_J= −40°C to +125°C

I_OUT= 0 μA

I_OUT= 0 μA, T_J= −40°C to +125°C

I_OUT= 1 μA

I_OUT= 1 μA, T_J= −40°C to +125°C

I_OUT= 100 μA

I_OUT= 100 μA, T_J= −40°C to +125°C

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 150 mA

I_OUT= 150 mA, T_J= −40°C to +125°C

EN = GND

5.5

I_GND

560

1250 nA

2.3 μA

1800 nA

2.8

4.5

5.8

860

2.6

μA

SHUTDOWN CURRENT

I_GND-SD

EN = GND, T_J= −40°C to +125°C

OUTPUT VOLTAGE ACCURACY

V_OUT

I_OUT= 10 mA

0 μA < I_OUT< 150 mA, V_IN= (V_OUT+ 0.5 V) to 5.5 V

0 μA < I_OUT< 150 mA, V_IN= (V_OUT+ 0.5 V) to 5.5 V,

T_J= −40°C to +125°C

−1

−2

−3.5

+3.5

ADJUSTABLE-OUTPUT VOLTAGE

ACCURACY (ADP161)¹

V_ADJ

I_OUT= 10 mA

0.99 1.0

1.01

0 μA < I_OUT< 150 mA, V_IN= (V_OUT+ 0.5 V) to 5.5 V

0 μA < I_OUT< 150 mA, V_IN= (V_OUT+ 0.5 V) to 5.5 V,

T_J= −40°C to +125°C

0.98

0.97

1.02

1.03

REGULATION

Line Regulation

Load Regulation²

∆V_OUT/∆V_IN

V_IN= (V_OUT+ 0.5 V) to 5.5 V, T_J= −40°C to +125°C

−0.1

+0.1

0.01

%/V

%/mA

∆V_OUT/∆I_OUTI_OUT= 100 ꢀA to 150 mA

I_OUT= 100 ꢀA to 150 mA, T_J= −40°C to +125°C

0.004

DROPOUT VOLTAGE³

4-Ball WLCSP

V_OUT= 3.3 V

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 150 mA

I_OUT= 150 mA, T_J= −40°C to +125°C

I_OUT= 10 mA

I_OUT= 10 mA, T_J= −40°C to +125°C

I_OUT= 150 mA

I_OUT= 150 mA, T_J= −40°C to +125°C

2.2 V ≤ V_IN≤ 5.5 V, ADJ connected to VOUT

V_OUT= 2.8 V, R_LOAD= ∞, ADP160 only

V_OUT= 3.3 V

V_DROPOUT

105

195

5-Lead TSOT

120

225

600

500

ADJ INPUT BIAS CURRENT (ADP161)

ACTIVE PULL-DOWN RESISTANCE

START-UP TIME⁴

ADJ_I-BIAS

T_SHUTDOWN

T_START-UP

I_LIMIT

300

1100

320

μs

CURRENT LIMIT THRESHOLD⁵

220

1.2

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

TS_SD

T_Jrising

150

°C

TS_SD-HYS

EN INPUT

En Input Logic High

EN Input Logic Low

EN Input Leakage Current

V_IH

V_IL

V_I-LEAKAGE

2.2 V ≤ V_IN≤ 5.5 V

EN = V_INor GND

EN = V_INor GND, T_J= −40°C to +125°C

μA

0.4

0.1

Rev. 0 | Page 3 of 20

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