Datasheet > ADP122UJZ-REDYKIT

ADP122UJZ-REDYKIT

更新时间： 2022-04-14 01:37:32

品牌	Logo	应用领域
亚德诺 - ADI		稳压器
页数	文件大小	规格书
24页	611K
描述
5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator

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ADP122UJZ-REDYKIT 数据手册

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ADP122/ADP123

Data Sheet

OUTLINE DIMENSIONS

2.90 BSC

2.80 BSC

1.60 BSC

0.95 BSC

1.90

BSC

0.90 MAX

0.70 MIN

1.00 MAX

0.20

0.08

8°

4°

0°

0.10 MAX

0.50

0.30

0.60

0.45

0.30

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 54. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

1.70

1.60

2.00

BSC SQ

1.50

0.65 BSC

0.175 REF

PIN 1 INDEX

AREA

EXPOSED

PAD

1.10

1.00

0.90

0.425

0.350

0.275

PIN 1

INDICATOR

(R 0.15)

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.60

0.55

0.50

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.35

0.30

0.25

0.20 REF

Figure 55. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD]

2.00 mm× 2.00 mm Body, Ultra Thin, Dual Lead

(CP-6-3)

Dimensions shown in millimeters

Rev. E | Page 20 of 24

1...17 18 192021 22 23 24

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