Datasheet > ADP120-1-ACBZ188R7

ADP120-1-ACBZ188R7

更新时间： 2024-01-10 23:16:29

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
20页	613K
描述
IC,VOLT REGULATOR,FIXED,+1.875V,CMOS,BGA,4PIN,PLASTIC

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ADP120-1-ACBZ188R7 数据手册

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ADP120

OUTLINE DIMENSIONS

2.90 BSC

2.80 BSC

1.60 BSC

PIN 1

0.95 BSC

1.90

BSC

0.90

0.87

0.84

1.00 MAX

0.20

0.08

8°

4°

0°

0.10 MAX

0.60

0.45

0.30

0.50

0.30

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH

THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.

Figure 50. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)

Dimensions shown in millimeters

0.660

0.600

0.540

0.860

0.820 SQ

0.780

A1 BALL

CORNER

SEATING

PLANE

0.280

0.260

0.240

0.40

BALL PITCH

TOP VIEW

(BALL SIDE DOWN)

BOTTOM VIEW

(BALL SIDE UP)

0.230

0.200

0.170

0.050 NOM

COPLANARITY

Figure 51. 4-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-4-2)

Dimensions shown in millimeters

ORDERING GUIDE

Output

Voltage (V)

Package

Option

Model

Temperature Range

–40°C to +125°C

Package Description

5-Lead TSOT

4-Ball WLCSP

Branding

L9R

L9Q

L9P

L9N

L8P

L8Q

L8R

L8S

L8T

L8U

L8V

ADP120-AUJZ12R7¹

ADP120-AUJZ15R7¹

ADP120-AUJZ18 R7¹

ADP120-AUJZ33R7¹

ADP120-1-ACBZ12R7¹

ADP120-1-ACBZ15R7¹

ADP120-1-ACBZ155R7¹

ADP120-1-ACBZ16R7¹

ADP120-1-ACBZ165R7¹

ADP120-1-ACBZ17R7¹

ADP120-1-ACBZ175R7¹

1.2

1.5

1.8

3.3

UJ-5

1.2

1.5

1.55

1.6

1.65

1.7

CB-4-2

1.75

Rev. 0 | Page 18 of 20

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