ADP1147-3.3/ADP1147-5
ILOAD × % duty cycle × VDROP = Diode Loss
Losses are encountered in all elements of the circuit, but the
four major sources for the circuit shown in Figure 1 are:
Figure 6 indicates the distribution of losses versus load cur-
rent in a typical ADP1147 switching regulator circuit. With
medium current loads the gate charge current is responsible
for a substantial amount of efficiency loss. At lower loads the
gate charge losses become large in comparison to the load,
and result in unacceptable efficiency levels. When low load
currents are encountered the ADP1147 employs a power
savings mode to reduce the effects of the gate loss. In the
power savings mode of operation the dc supply current is the
major source of loss and becomes a greater percentage as the
output current decreases.
1. T he ADP1147 dc bias current.
2. T he MOSFET gate charge current.
3. T he I2 × R losses.
4. T he voltage drop of the Schottky diode.
1. T he ADP1147’s dc bias current is the amount of current that
flows into VIN of the device minus the gate charge current.
With VIN = 10 volts, the dc supply current to the device is
typically 160 µA for a no load condition, and increases pro-
portionally with load to a constant of 1.6 mA in the continu-
ous mode of operation. Losses due to dc bias currents increase
as the input voltage VIN is increased. At VIN = 10 volts the dc
bias losses are usually less than 1% with a load current
greater than 30 mA. When very low load currents are
encountered the dc bias current becomes the primary point
of loss.
Losses at higher loads are primarily due to I2R and the
Schottky diode. All other variables such as capacitor ESR
dissipation, MOSFET switching, and inductor core losses
typically contribute less than 2% additional loss.
Cir cuit D esign Exam ple
In using the design example below assumptions are as follows:
2. T he MOSFET gate charge current is due to the switching of
the power MOSFET ’s gate capacitance. As the MOSFET ’s
gate is switched from a low to a high and back to a low again,
charge impulses dQ travel from VIN to ground. T he current
out of VIN is equal to dQ/dt and is usually much greater than
the dc supply current. When the device is operating in the
continuous mode the I gate charge is = f (QP). T ypically a
P-channel power MOSFET with an RDS on of 135 mΩ will
have a gate charge of 40 nC. With a 100 kH z, switching
frequency in the continuous mode, the I gate charge would
VIN = 5 Volts
VOUT = 3.3 Volts
VDIODE drop (VD) = 0.4 Volts
IMAX OUT = 1 Amp
Max switching frequency (f) = 100 kHz.
T he values for RSENSE, CT and L can be calculated based on the
above assumptions.
RSENSE = 100 mV/1 Amp = 100 mΩ.
tOFF time = (1/100 kHz) × [1 – (3.7/5.4)] = 3.15 µs.
4
equate to 4 mA or about a 2%–3% loss with a V of 10 volts.
CT = 3.15 µs /(1.3 × 10 ) = 242 pF.
IN
L = 5.1 × 10 5 × 0.1 Ω × 242 pF × 3.3 V = 41 µH.
If we further assume:
It should be noted that gate charge losses increase with
switching frequency or input voltage. A design requiring the
highest efficiency can be obtained by using more moderate
switching frequencies.
1. T he data is specified at +25°C.
2. MOSFET max power dissipation (PP) is limited to 250 mW.
3. MOSFET thermal resistance is 50°C/W.
3. I2 × R loss is a result of the combined dc circuit resistance
and the output load current. T he primary contributors to
circuit dc resistance are the MOSFET , the Inductor and
4. T he normalized RDS(ON) vs. temperature approximation (δP)
is 0.007/°C.
R
SENSE. In the continuous mode of operation the average
output current is switched between the MOSFET and the
Schottky diode and a continuous current flows through the
inductor and RSENSE. T herefore the RDS(ON) of the MOSFET
is multiplied by the on portion of the duty cycle. T he result is
then combined with the resistance of the Inductor and
T his results in 250 mW × 50°C per watt = 12.5°C of MOSFET
heat rise. If the ambient temperature TA is 50°C, a junction
temperature of 12.5°C +50°C, T A = 62.5°C. δP = 0.007 ×
(62.5°C –25°C) = 0.2625
We can now determine the required RDS(ON) for the MOSFET :
R
SENSE. T he following equations and example show how to
approximate the I2 × R losses of a circuit.
RDS(ON) = 5(0.25)/3.3 (1)2 (1.2625) = 300 mΩ
RDS(ON) × (Duty Cycle) + RINDUCTOR + RSENSE = R
T he above requirements can be met with the use of a P-channel
IRF7204 or an Si9430.
2
ILOAD × R = PLOSS
When VOUT is short circuited the power dissipation of the
Schottky diode is at worst case and the dissipation can rise
greatly. T he following equation can be used to determine the
power dissipation:
VOUT × ILOAD = POUT
PLOSS/POUT × 100 = % I2 × RLOSS
.
With the duty cycle = 0.5, RINDUCTOR = 0.15, RSENSE = 0.05
and ILOAD = 0.5 A. T he result would be a 3% I2R loss. T he
effects of I2R losses causes the efficiency to fall off at higher
output currents.
PD = ISC(AVG) × VDIODE Drop
A 100 mΩ RSENSE resistor will yield an ISC(AVG) of 1 A. With a
forward diode drop of 0.4 volts a 400 milliwatt diode power
dissipation results.
4. At high current loads the Schottky diode can be a substantial
point of power loss. T he diode efficiency is further reduced
by the use of high input voltages. T o calculate the diode loss,
the load current should be multiplied by the duty cycle of the
diode times the forward voltage drop of the diode.
T he rms current rating needed for CIN will be at least 0.5 A over
the temperature range.
–10–
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