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ADN2890 PDF预览

ADN2890

更新时间: 2024-01-26 13:33:38
品牌 Logo 应用领域
亚德诺 - ADI 放大器
页数 文件大小 规格书
12页 263K
描述
3.3 V 2.7 Gb/s Limiting Amplifier

ADN2890 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC16,.12SQ,20针数:16
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.33.00.01风险等级:5.73
JESD-30 代码:S-XQCC-N16JESD-609代码:e0
长度:3 mm湿度敏感等级:3
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC16,.12SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):220
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:ATM/SONET/SDH ICs
最大压摆率:0.054 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:TELECOM CIRCUIT
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15) - with Silver (Ag) barrier
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:3 mmBase Number Matches:1

ADN2890 数据手册

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ADN2890  
THEORY OF OPERATION  
LIMAMP  
RECEIVED SIGNAL STRENGTH INDICATOR (RSSI)  
Input Buffer  
The ADN2890 has an on-chip RSSI circuit that automatically  
detects the average received power based on a direct measure-  
ment of the PIN photodiodes current. The photodiode bias is  
supplied by the ADN2890, which allows a very accurate, on-  
chip, average power measurement based on the amount of  
current supplied to the photodiode. The output of the RSSI is a  
current that is directly proportional to the average amount of  
PIN photodiode current. Placing a resistor between the  
RSSI_OUT pin and GND converts the current to a GND  
referenced voltage. This function eliminates the need for  
external RSSI circuitry in SFF-8472 compliant optical receivers.  
The limiting amplifier has differential inputs (PIN/NIN), with  
an internal 50 Ω termination. The ROSA (receive optical sub-  
assembly) is typically ac-coupled to the ADN2890 inputs,  
although dc coupling is possible.  
An internal offset correction loop requires that a capacitor be  
connected between the CAZ1 and CAZ2 pins. A 0.01 µF  
capacitor provides a low frequency cutoff of 2 kHz.  
CML Output Buffer  
The ADN2890 provides CML outputs, OUTP/OUTN. The  
outputs are internally terminated with 50 Ω to VCC.  
SQUELCH MODE  
The outputs can be kept at a static voltage by driving the  
SQUELCH pin to a logic high. The SQUELCH pin can be  
driven directly by the LOS pin, which automatically disables the  
LIMAMP outputs in situations with no data input.  
Driving the SQUELCH input to a logic high disables the  
limiting amplifier outputs. The SQUELCH input can be  
connected to the LOS output to keep the limiting amplifier  
outputs at a static voltage level anytime the input level to the  
limiting amplifier drops below the programmed LOS threshold.  
LOSS OF SIGNAL (LOS) DETECTOR  
The receiver front-end LOS detector circuit indicates when the  
input signal level has fallen below the user-adjustable threshold.  
The threshold is set by a resistor connected between the  
THRADJ pin and VEE. The ADN2890 LOS circuit has a trip  
point down to <3.0 mV with >3 dB electrical hysteresis to  
prevent chatter at the LOS output. The LOS output is an open-  
collector output that must be pulled up externally with a 4.7 kΩ  
to 10 kΩ resistor.  
Rev. 0 | Page 8 of 12  

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