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ADN2860

更新时间： 2024-02-15 09:32:18
品牌 Logo 应用领域
亚德诺 - ADI 电位器存储
页数 文件大小 规格书
15页 1125K
描述
3-Channel Digital Potentiometer with Nonvolatile Memory

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ADN2860 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFN包装说明：4 X 4 MM, LFCSP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.91其他特性：IT CAN ALSO OPERATE FROM A 3 TO 5.5V SINGLE SUPPLY
标称带宽：0.125 kHz控制接口：2-WIRE SERIAL
转换器类型：DIGITAL POTENTIOMETERJESD-30 代码：S-XQCC-N24
JESD-609代码：e0长度：4 mm
标称负供电电压：-2.5 V功能数量：1
位置数：512端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：VQCCN
封装等效代码：LCC24,.16SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3/5 V认证状态：Not Qualified
电阻定律：LINEAR最大电阻容差：30%
最大电阻器端电压：2.5 V最小电阻器端电压：-2.5 V
座面最大高度：1 mm子类别：Digital Potentiometers
标称供电电压：2.5 V表面贴装：YES
标称温度系数：35 ppm/ °C温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED标称总电阻：250000 Ω
宽度：4 mmBase Number Matches：1

ADN2860 数据手册

 浏览型号ADN2860的Datasheet PDF文件第6页浏览型号ADN2860的Datasheet PDF文件第7页浏览型号ADN2860的Datasheet PDF文件第8页浏览型号ADN2860的Datasheet PDF文件第10页浏览型号ADN2860的Datasheet PDF文件第11页浏览型号ADN2860的Datasheet PDF文件第12页 
Preliminary Technical Data  
ADN2860  
RDAC I2C Interface Description (cont’d)  
S
0
1
0
1
1
A
1
A
0
0
A
CMD/  
W
C
3
C
2
C
1
C
0
A
2
A
1
A
0
A
P
R
R
RDAC Slave Address  
0 Write  
1 Cmd  
Figure 11. RDAC Command Write (Dummy Write)  
RDAC Command Table (CMD/W=1)  
C3 C2 C1 C0  
Command Description  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NOP  
Load EEPROM to RDAC*  
Store RDAC to EEPROM  
Decrement RDAC 6dB  
Decrement All RDACs 6dB  
Decrement RDAC One Step  
Decrement All RDACs One Step  
Reset: Load EEPROM to all RDACs  
Increment RDAC 6dB  
Increment All RDAC 6dB  
Increment RDAC One Step  
Increment All RDAC One Step  
0 to reserved  
1
Table 3. RDAC Commands  
* This command leaves the device in the EEPROM Read power state. Issue the NOP  
command to return the device to the idle state.  
interface section, is required to determine whether the write  
cycle has been completed.  
RDAC Interface Operation  
Each programmable resistor wiper setting is controlled by  
specific RDAC registers, as shown in the RDAC Register  
Address Table (table 1). Each RDAC register corresponds to an  
EEPROM memory location, which provides non-volatile wiper  
storage functionality.  
RDAC Read  
The ADN2860 provides two RDAC read operations. The first,  
shown in figure 9 reads the contents of the current RDAC  
address counter. Figure 10 illustrates the second read operation.  
This operation allows users to specify which RDAC register to  
read by first issuing a “dummy write” command to change the  
RDAC address pointer, and then proceeding with the RDAC  
read operation at the new address location.  
RDAC registers and their corresponding EEPROM memory  
locations can be programmed and read independently from each  
other. The RDAC register can be refreshed by the EEPROM  
locations either with a hardware reset via pin 1, or by issuing  
one of the various RDAC register load commands shown in the  
RDAC command table (table 3).  
The read-only RDAC EEPROM memory locations can also be  
read by using the address and bits specified in the RDAC Read-  
Only EEPROM Address Table (table 2).  
RDAC Write  
Setting the wiper position requires an RDAC write operation,  
shown in figure 8. RDAC write operations follow a format  
similar to the EEPROM write interface. The only difference  
between an RDAC write and an EEPROM write operation is the  
use of an RDAC address byte in place of the memory address  
used in the EEPROM write operation. The RDAC address byte  
is described in detail in the tables 1 and 2.  
RDAC Quick Commands  
Eleven shortcut “quick” commands are provided for easy  
manipulation of RDAC registers and their corresponding  
EEPROM memory locations. These commands are shown in  
table 3.  
The interface for issuing an RDAC quick command is shown in  
figure 11. All quick commands require Acknowledge polling to  
determine whether the command has finished executing.  
As with the EEPROM write operation, the RDAC write  
operation disables the I2C interface during the internal write  
cycle. Acknowledge polling, as described in the EEPROM I2C  
Page 9 of 15  
REV. PrD  
1...6789101112...15

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