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ADMC328TN PDF预览

ADMC328TN

更新时间: 2024-01-09 14:25:28
品牌 Logo 应用领域
亚德诺 - ADI 电机控制器
页数 文件大小 规格书
32页 236K
描述
28-Lead ROM-Based DSP Motor Controller with Current Sense

ADMC328TN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-28
针数:28Reach Compliance Code:not_compliant
风险等级:5.92地址总线宽度:
桶式移位器:YES边界扫描:NO
最大时钟频率:20 MHz外部数据总线宽度:
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:R-PDSO-G28JESD-609代码:e0
长度:17.9 mm低功率模式:NO
端子数量:28最高工作温度:105 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:2.65 mm
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADMC328TN 数据手册

 浏览型号ADMC328TN的Datasheet PDF文件第26页浏览型号ADMC328TN的Datasheet PDF文件第27页浏览型号ADMC328TN的Datasheet PDF文件第28页浏览型号ADMC328TN的Datasheet PDF文件第29页浏览型号ADMC328TN的Datasheet PDF文件第31页浏览型号ADMC328TN的Datasheet PDF文件第32页 
ADMC328  
MODECTRL (R/W)  
15 14 13 12  
11 10  
9
8
7
6
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2015)  
0
0
0
0
0
0
0
0
0
0
0 = OFFSET MODE  
1 = INDEPENDENT MODE  
AUXILIARY  
PWM SELECT  
ADC MUX CONTROL  
00 VAUX0  
01 VAUX1  
10 VAUX2  
11 VAUX3  
ADC  
COUNTER  
SELECT  
0 = CLKIN RATE  
1 = CLKOUT RATE  
PWMTRIP  
INTERRUPT  
0 = DISABLE  
1 = ENABLE  
PWMSYNC  
INTERRUPT  
0 = DISABLE  
1 = ENABLE  
SPORT1 DATA  
RECEIVE  
SELECT  
0 = DR1A  
1 = DR1B  
SPORT1 MODE  
SELECT  
0 = SPORT  
1 = UART  
0 = SINGLE UPDATE MODE  
1 = DOUBLE UPDATE MODE  
PWM UPDATE  
MODE SELECT  
SYSSTAT (R)  
15 14 13 12  
11 10  
9
0
8
7
6
0
5
0
4
3
2
1
1
0
DM (0x2016)  
0
0
0
0
0
0
0
0
0
PWMTRIP  
PIN STATUS  
0 = LOW  
1 = HIGH  
0 = 1ST HALF OF PWM  
CYCLE  
1 = 2ND HALF OF PWM  
CYCLE  
0 = NORMAL  
1 = WATCHDOG RESET  
OCCURRED  
PWM TIMER  
STATUS  
WATCHDOG  
STATUS  
IRQFLAG (R)  
15 14 13 12  
11 10  
9
8
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2017)  
0
0
0
0
0
0
0
0
0
PWMTRIP INTERRUPT  
0 = NO INTERRUPT  
1 = INTERRUPT  
OCCURRED  
PWMSYNC INTERRUPT  
WDTIMER (W)  
15 14 13 12  
11 10  
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
DM (0x2018)  
0
0
0
0
0
0
Figure 27. Configuration of Status Registers  
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these  
bits should always be written as shown.  
REV. B  
–30–  

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