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ADM9690ARN-REEL PDF预览

ADM9690ARN-REEL

更新时间: 2024-01-02 07:17:37
品牌 Logo 应用领域
亚德诺 - ADI 监控
页数 文件大小 规格书
6页 78K
描述
IC 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, SOIC-8, Power Management Circuit

ADM9690ARN-REEL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.12
可调阈值:NO模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
信道数量:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.3 V
标称供电电压 (Vsup):5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

ADM9690ARN-REEL 数据手册

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ADM9690  
POWER SUPPLY AND WATCHDOG MONITORING  
CIRCUIT  
provide a power-on reset signal for the µP while RESET(2) is  
used to hold additional circuitry in a reset state until the µP has  
regained control following a power-up.  
The ADM9690 contains a power supply voltage monitoring  
comparator and a watchdog timer monitor. Either VMON drop-  
ping outside tolerance or the watchdog timer timing out results  
in a reset sequence as discussed below. Two reset outputs are  
provided. RESET(1) and RESET(2).  
The guaranteed minimum and maximum thresholds for the  
ADM9690 are 4.3 V and 4.5 V.  
Watchdog Timer RESET  
The watchdog timer circuit monitors the activity of the micro-  
processor in order to check that it is not stalled in an infinite  
loop. An output line on the processor may be used to toggle the  
Watchdog Input (WDI) line. If this line is not toggled within the  
selected timeout period, both RESET outputs are taken active  
(low). RESET(1) remains low for 50 ms and RESET(2) re-  
mains low for an additional 10 ms . Each transition (either  
positive-going or negative-going) of WDI after RESET(1) has  
gone inactive restarts the watchdog timer. The actual watchdog  
timeout period is adjustable using SEL1 and SEL2. Four timeout  
periods are selectable. Please refer to Table I.  
POWER FAIL/POWER-ON RESET  
When VMON falls below the reset threshold (4.4 V) both RESET  
outputs are forced low immediately.  
On power-up, RESET(1) will remain low for 50 milliseconds  
after VMON rises above the reset threshold. This provides a  
power-on reset for the microprocessor. RESET(2) remains  
active low for an additional 10 ms. RESET(1) is intended to  
V
CC  
V
ADM9690  
MON  
The watchdog timer is restarted at the end of RESET(1)  
(RESET(1) going high), whether the reset was caused by lack of  
activity on WDI or by VMON falling below the reset threshold.  
4.31V  
RESET(1)  
RESET(1)  
OSC SEL1  
OSC SEL2  
TIMER  
WATCHDOG  
TIMEBASE  
Table I.  
RESET(2)  
TIMER  
RESET(2)  
Watchdog Timeout  
Period tWD (ms)  
WATCHDOG  
TRANSITION  
DETECTOR  
WATCHDOG  
INPUT (WDI)  
SEL2  
SEL1  
0
0
1
1
0
1
0
1
0.75  
1.5  
12.5  
25  
GND  
Figure 6. Functional Block Diagram  
WDI  
V
MON  
tWD  
t1  
t1  
RESET(1)  
RESET(2)  
RESET(1)  
t2  
t2  
RESET(2)  
Figure 7. Power-On RESET Timing  
Figure 8. Watchdog RESET Timing  
REV. A  
5–  

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