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ADM8840ACP-REEL7 PDF预览

ADM8840ACP-REEL7

更新时间： 2024-02-14 21:54:18
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER /
页数 文件大小 规格书
11页 847K
描述
SWITCHED CAPACITOR REGULATOR, CQCC32, 5 X 5 MM, LFCSP-32

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ADM8840ACP-REEL7 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Active零件包装代码：QFN
包装说明：VQCCN,针数：32
Reach Compliance Code：unknown风险等级：5.23
Is Samacsys：N模拟集成电路 - 其他类型：SWITCHED CAPACITOR REGULATOR
最大输入电压：3.6 V最小输入电压：2.7 V
标称输入电压：3.3 VJESD-30 代码：S-CQCC-N32
JESD-609代码：e0长度：5 mm
湿度敏感等级：3功能数量：1
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：VQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：240
认证状态：COMMERCIAL座面最大高度：0.9 mm
表面贴装：YES切换器配置：TRIPLER
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5 mm
Base Number Matches：1

ADM8840ACP-REEL7 数据手册

 浏览型号ADM8840ACP-REEL7的Datasheet PDF文件第3页浏览型号ADM8840ACP-REEL7的Datasheet PDF文件第4页浏览型号ADM8840ACP-REEL7的Datasheet PDF文件第5页浏览型号ADM8840ACP-REEL7的Datasheet PDF文件第7页浏览型号ADM8840ACP-REEL7的Datasheet PDF文件第8页浏览型号ADM8840ACP-REEL7的Datasheet PDF文件第9页 
PRELIMINARY TECHNICAL DATA  
ADM8840  
PIN FUNCTION DESCRIPTION  
Pin  
Mnemonic  
Function  
1ꢀ3±  
C1+ꢀC1-  
External capacitor C1 is connected between these pins. A 3.3␮F capacitor is  
recommended.  
±ꢀ±±  
3
VCC  
Positive Supply Voltage Input. Connect this pin to 3V supply. A 4.7  
decoupling capacitor should be attached close to pin ±.  
␮F  
VOUT  
Voltage Doubler Output. This was derived by doubling the 3V supply. A 3.3␮F  
capacitor to ground is required on this pin.  
4
5
6
+5VOUT  
+5VIN  
+5.0V output pin. This was derived by doubling and regulating the +3V supply.  
A ±.±␮F capcitor to ground is required on this pin to stabilise the regulator.  
+5.0V input pin. This is the input to the voltage tripler and inverter charge pump  
circuits.  
S H D N  
Digital Input. 3V CMOS Logic. Active low shutdown control. This shuts down  
the timing generator and enables the discharge circuit to dissipate the charge on  
the voltage outputsꢀ thus driving them to 0V.  
7
DAC1_SD  
DAC1_IN  
GND  
Switches over to external DAC1 input when asserted.  
Input for external DAC1 signal.  
Device Ground Pin.  
9
17ꢀ 31  
13  
SCLK  
External Clock Input. Used to load DAC 1 with COM Voltage amplitude and  
DAC ± with COM Centre Voltage.  
1±  
11  
DATA  
Digital Data Input to both DAC’s 1 and ±.  
CS / LDAC  
Dual function pin.  
1.Chip Select. Digital Input Logic. Chip Select for Digital Interface.  
±. Load DAC. Digital Input Logic. DAC’s 1 and ± perform a conversion on a  
low-to-high transition.  
18  
16  
14  
COM_IN  
Clock Input from digital controller chip. This input is level shiftedꢀ offset and  
inverted to provide a COM Voltage output swing at a frequency of the COM_IN  
input.  
COM_OUT_AC  
COM_OUT  
COM_OUT_AC outputs the COM_IN signal inverted and level shifted by the  
value programmed on DAC 1. A 4.7␮F capacitor is connected between this pin  
and COM_OUT.  
The AC output on COM_OUT_AC is added to the center voltage programmed on  
DAC± so that the desired amplitudeꢀ centered about the correct center voltage  
appears on COM_OUT. The load capacitance seen by this pin is the bulk capaci  
tance of the panelꢀ typically ±0nF.  
8
DAC±_SD  
Switches over to external DAC± input when asserted.  
Input for external DAC± signal.  
10  
15  
DAC±_IN  
TRANS_OUT  
Level Translator Reference Output Voltage. This is the voltage that the value on  
DAC 1 is gained up to to provide the upper voltage for the Level Translator.  
voltage of between 4.0V and 7.0V can be output here. A 4.7␮F cap is  
recommended for this pin.  
A
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the ADM8840 features proprietary ESD protection circuitryꢀ permanent damage  
may occur on devices subjected to high energy electrostatic discharges. Thereforeꢀ proper  
ESD precautions are recommended to avoid performance degradation or loss of functionality.  
REV. PrG 2/03  
–5–  
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