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ADM8694

更新时间： 2024-02-21 06:20:15
品牌 Logo 应用领域
亚德诺 - ADI 微处理器监控
页数 文件大小 规格书
16页 183K
描述
Microprocessor Supervisory Circuits

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ADM8694 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP,针数：8
Reach Compliance Code：unknown风险等级：5.17
可调阈值：NO模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
信道数量：2功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3.9 mm
Base Number Matches：1

ADM8694 数据手册

 浏览型号ADM8694的Datasheet PDF文件第4页浏览型号ADM8694的Datasheet PDF文件第5页浏览型号ADM8694的Datasheet PDF文件第6页浏览型号ADM8694的Datasheet PDF文件第8页浏览型号ADM8694的Datasheet PDF文件第9页浏览型号ADM8694的Datasheet PDF文件第10页 
ADM8690–ADM8695  
Table I. AD M8691, AD M8693, AD M8695 Reset P ulse Width and Watchdog Tim eout Selections  
Watchdog Tim eout P eriod  
Im m ediately  
Reset Active P eriod  
O SC SEL  
O SC IN  
Norm al  
After Reset  
AD M8691/AD M8693  
AD M8695  
Low  
Low  
External Clock Input  
External Capacitor  
1024 CLKS  
400 ms × C/47 pF  
100 ms  
4096 CLKS  
1.6 s × C/47 pF  
1.6 s  
512 CLKS  
200 ms × C/47 pF  
50 ms  
2048 CLKS  
520 ms × C/47 pF  
200 ms  
Floating or High Low  
Floating or High Floating or High  
1.6 s  
1.6 s  
50 ms  
200 ms  
NOT E  
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. T he nominal  
internal oscillator frequency is 10.24 kHz. T he nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF)  
On the ADM8690/ADM8692 the watchdog timeout period is  
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.  
On the ADM8694 the watchdog timeout period is also 1.6 sec-  
onds but the reset pulse width is fixed at 200 ms. The ADM8691/  
ADM8693/ADM8695 allow these times to be adjusted as  
shown in T able I. Figure 4 shows the various oscillator configu-  
rations that can be used to adjust the reset pulse width and  
watchdog timeout period.  
8
7
OSC SEL  
ADM8691  
ADM8693  
ADM8695  
OSC IN  
C
OSC  
Figure 4b. External Capacitor  
T he internal oscillator is enabled when OSC SEL is high or  
floating. In this mode, OSC IN selects between the 1.6 second  
and 100 ms watchdog timeout periods. With OSC IN connected  
high or floating, the 1.6 second timeout period is selected; while  
with it connected low, the 100 ms timeout period is selected. In  
either case, immediately after a reset the timeout period is 1.6  
seconds. T his gives the microprocessor time to reinitialize the  
system. If OSC IN is low, then the 100 ms watchdog period be-  
comes effective after the first transition of WDI. T he software  
should be written such that the I/O port driving WDI is left in  
its power-up reset state until the initialization routines are com-  
pleted and the microprocessor is able to toggle WDI at the mini-  
mum watchdog timeout period of 70 ms.  
8
OSC SEL  
NC  
ADM8691  
ADM8693  
ADM8695  
7
OSC IN  
NC  
Figure 4c. Internal Oscillator (1.6 Second Watchdog)  
8
OSC SEL  
NC  
Watchdog O utput (WD O )  
T he Watchdog Output WDO (ADM8691/ADM8693/  
ADM8695) provides a status output which goes low if the  
watchdog timer “times out” and remains low until set high by  
the next transition on the Watchdog Input. WDO is also set  
high when VCC goes below the reset threshold.  
ADM8691  
ADM8693  
ADM8695  
7
OSC IN  
Figure 4d. Internal Oscillator (100 m s Watchdog)  
8
OSC SEL  
ADM8691  
ADM8693  
ADM8695  
CLOCK  
0 TO 500kHz  
7
OSC IN  
Figure 4a. External Clock Source  
REV. 0  
–7–  
1...45678910...16

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