ADM8693AN

更新时间： 2024-02-24 15:51:44

品牌	Logo	应用领域
亚德诺 - ADI		微处理器光电二极管监控
页数	文件大小	规格书
16页	209K
描述
Microprocessor Supervisory Circuits

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技术参数
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ADM8693AN 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.4	针数：	16
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.15
其他特性：	RESET THRESHOLD VOLTAGE IS 4.4V	可调阈值：	NO
模拟集成电路 - 其他类型：	POWER SUPPLY MANAGEMENT CIRCUIT	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3	长度：	10.3 mm
湿度敏感等级：	1	信道数量：	2
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP16,.4	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	峰值回流温度（摄氏度）：	260
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	2.65 mm	子类别：	Power Management Circuits
最大供电电流 (Isup)：	0.2 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	7.5 mm	Base Number Matches：	1

ADM8693AN 数据手册

ADM8690–ADM8695

P IN FUNCTIO N D ESCRIP TIO N

Mnem onic

Function

V_CC

Power Supply Input: +5 V Nominal.

Backup Battery Input.

V_{BAT T}

V_OUT

Output Voltage, V_CCor V_{BAT T}is internally switched to V_OUTdepending on which is at the highest potential. V_OUT

can supply up to 100 mA to power CMOS RAM. Connect V_OUTto V_CCif V_OUTand V_{BAT T}are not used.

GND

0 V. Ground reference for all signals.

RESET

Logic Output. RESET goes low if

1. V_CCfalls below the Reset T hreshold

2. T he watchdog timer is not serviced within its timeout period.

The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8694/ADM8695 and 4.4 V for the ADM8692

and ADM8693. RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8694/

ADM8695) after V_CCreturns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is

enabled but not serviced within its timeout period. The RESET pulse width can be adjusted on the ADM8691/ADM8693/

ADM8695 as shown in T able I. T he RESET output has an internal 3 µA pull up, and can either connect

to an open collector Reset bus or directly drive a CMOS gate without an external pull-up resistor.

WDI

Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout

period, RESET pulses low and WDO goes low. T he timer resets with each transition on the WDI line. T he watchdog

timer may be disabled if WDI is left floating or is driven to midsupply.

PFI

Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V, PFO

goes low. Connect PFI to GND or V_OUTwhen not used.

PFO

Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. T he

comparator is turned off and PFO goes low when V_CCis below V_{BAT T}

CE_IN

Logic Input. T he input to the CE gating circuit. Connect to GND or V_OUTif not used.

CE_OUT

Logic Output. CE_OUTis a gated version of the CE_INsignal. CE_OUTtracks CE_INwhen V_CCis above the reset

threshold. If V_CCis below the reset threshold, CE_OUTis forced high. See Figures 5 and 6.

BAT T ON

Logic Output. BAT T ON goes high when V_OUTis internally switched to the V_{BAT T}input. It goes low when V_OUT

is internally switched to V_CC. T he output typically sinks 35 mA and can directly drive the base of an external

PNP transistor to increase the output current above the 100 mA rating of V_OUT

LOW LINE Logic Output. LOW LINE goes low when V_CCfalls below the reset threshold. It returns high as soon as V_CCrises

above the reset threshold.

RESET

Logic Output. RESET is an active high output. It is the inverse of RESET.

OSC SEL

Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets

the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,

is enabled. OSC SEL has a 3 µA internal pull-up (see T able I).

OSC IN

Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external

capacitor can be connected between OSC IN and GND. T his sets both the reset active pulse timing and the watch-

dog timeout period (see T able I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled

and the reset active time is fixed at 50 ms typ. (ADM8691/ADM8693) or 200 ms typ (ADM8695). In this mode the

OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout

period immediately after a reset is 1.6 s typical.

WDO

Logic Output. T he Watchdog Output, WDO, goes low if WDI remains either high or low for longer than the

watchdog timeout period. WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,

the watchdog timer is disabled and WDO remains high. WDO also goes high when LOW LINE goes low.

–4–

REV. 0

1 2 345 6 7...16

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与ADM8693AN相关器件

型号	品牌	描述	获取价格	数据表
ADM8693ANZ	ADI	IC 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16, ROHS COMPLIANT, PLASTIC, MS-001AB, DIP-1	获取价格
ADM8693ARN	ADI	Microprocessor Supervisory Circuits	获取价格
ADM8693ARN-REEL	ADI	IC 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16, MS-012AC, SOIC-16, Power Management Circ	获取价格
ADM8693ARU	ADI	Microprocessor Supervisory Circuits	获取价格
ADM8693ARU	ROCHESTER	2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16, MO-153AB, TSSOP-16	获取价格
ADM8693ARUZ	ADI	IC 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16, ROHS COMPLIANT, MO-153AB, TSSOP-16, Powe	获取价格

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