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ADM8318WCY46ARJZR7 PDF预览

ADM8318WCY46ARJZR7

更新时间： 2024-01-05 07:52:31
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
15页 275K
描述
Supervisory Circuit with Watchdog, Active-Low and Active-High Push-Pull Reset Outputs

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ADM8318WCY46ARJZR7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：LSSOP, SOP5,.12,37
针数：5Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：1.69可调阈值：NO
模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUITJESD-30 代码：R-PDSO-G5
JESD-609代码：e3长度：2.9 mm
湿度敏感等级：1信道数量：1
功能数量：1端子数量：5
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：SOP5,.12,37封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
座面最大高度：1.45 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：0.9 V标称供电电压 (Vsup)：3.6 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：0.95 mm端子位置：DUAL
阈值电压标称：+4.63V处于峰值回流温度下的最长时间：30
宽度：1.6 mmBase Number Matches：1

ADM8318WCY46ARJZR7 数据手册

 浏览型号ADM8318WCY46ARJZR7的Datasheet PDF文件第7页浏览型号ADM8318WCY46ARJZR7的Datasheet PDF文件第8页浏览型号ADM8318WCY46ARJZR7的Datasheet PDF文件第9页浏览型号ADM8318WCY46ARJZR7的Datasheet PDF文件第11页浏览型号ADM8318WCY46ARJZR7的Datasheet PDF文件第12页浏览型号ADM8318WCY46ARJZR7的Datasheet PDF文件第13页 
ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/ADM8322  
Data Sheet  
THEORY OF OPERATION  
CIRCUIT DESCRIPTION  
OPEN-DRAIN RESET OUTPUT  
The ADM8316/ADM8318/ADM8319/ADM8320/ADM8321/  
ADM8322 provide microprocessor supply voltage supervision  
by controlling the microprocessor reset input. Code execution  
errors are avoided during power-up, power-down, and brownout  
conditions by asserting a reset signal when the supply voltage  
is below a preset threshold and by allowing supply voltage  
stabilization with a fixed timeout reset delay after the supply  
voltage rises above the threshold. In addition, problems with  
microprocessor code execution can be monitored and corrected  
with a watchdog timer (ADM8316/ADM8318/ADM8320/  
ADM8321). If the user detects a problem with system operation, a  
manual reset input is available (ADM8316/ADM8319/ADM8320/  
ADM8322) to reset the microprocessor, for example, by means  
of an external push-button switch.  
The ADM8320/ADM8321/ADM8322 have an active low, open-  
drain reset output. This output structure requires an external  
pull-up resistor to connect the reset output to a voltage rail no  
higher than VCC. A resistor that complies with the logic low and  
logic high voltage level requirements of the microprocessor  
RESET  
while supplying input current and leakage paths on the  
line is recommended. A 10 kΩ resistor is adequate in most  
situations.  
MANUAL RESET INPUT  
The ADM8316/ADM8319/ADM8320/ADM8322 feature a manual  
MR  
reset input ( ), which when driven low, asserts the reset output.  
MR  
When  
for the duration of the reset active timeout period before  
MR  
transitions from low to high, the reset remains asserted  
PUSH-PULL RESET OUTPUT  
deasserting. The  
so that the input is always high when unconnected. An external  
MR  
input has a 75 kΩ, internal pull-up resistor  
The ADM8316 features an active low push-pull reset output,  
whereas the ADM8321/ADM8322 have active high push-pull  
reset outputs. The ADM8318/ADM8319 feature dual active low  
and active high push-pull reset outputs. For active low and active  
high outputs, the reset signal is guaranteed to be valid for VCC  
down to 0.9 V.  
push-button switch can be connected between  
and ground  
so that the user can generate a reset. Debounce circuitry for this  
purpose is integrated on chip. Noise immunity is provided on  
MR  
the  
input, and fast, negative going transients of up to 100 ns  
MR  
(typical) are ignored. A 0.1 µF capacitor between  
provides additional noise immunity.  
and ground  
The reset output is asserted when VCC is below the reset threshold  
MR  
(VTH), when  
is driven low, or when WDI is not serviced  
WATCHDOG INPUT  
within the watchdog timeout period (tWD). The reset output  
remains asserted for the duration of the reset active timeout  
period (tRP) after VCC rises above the reset threshold, after  
transitions from low to high, or after the watchdog timer times  
out. Figure 20 illustrates the behavior of the reset outputs.  
The ADM8316/ADM8318/ADM8320/ADM8321 feature a  
watchdog timer that monitors microprocessor activity. A timer  
circuit is cleared with every low-to-high or high-to-low logic  
transition on the watchdog input pin (WDI), which detects pulses  
as short as 50 ns. If the timer counts through the preset watchdog  
timeout period (tWD), a reset is asserted. The microprocessor is  
required to toggle the WDI pin to avoid asserting the reset pin.  
Failure of the microprocessor to toggle WDI within the timeout  
period, therefore, indicates a code execution error, and the reset  
pulse generated restarts the microprocessor in a known state.  
MR  
V
CC  
V
V
TH  
TH  
V
CC  
1V  
0V  
V
CC  
RESET  
RESET  
tRP  
tRD  
0V  
V
CC  
As well as logic transitions on WDI, the watchdog timer is also  
cleared by a reset assertion due to an undervoltage condition on  
tRP  
1V  
0V  
tRD  
MR  
V
CC or due to  
being pulled low. When a reset asserts, the  
Figure 20. Reset Timing Diagram  
watchdog timer clears and does not begin counting again until  
the reset deassserts. The watchdog timer can be disabled by  
leaving WDI floating or by tristating the WDI driver.  
V
CC  
V
TH  
V
CC  
1V  
0V  
V
CC  
RESET  
WDI  
tRP  
tWD  
tRP  
0V  
V
CC  
0V  
Figure 21. Watchdog Timing Diagram  
Rev. C | Page 10 of 15  
 
 
 
 
 
 
 
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