Datasheet > ADM706R_15

ADM706R_15

更新时间： 2022-02-26 10:26:31

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	333K
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Microprocessor Supervisory Circuits

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数据手册

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ADM706R_15 数据手册

Data Sheet ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

RESET

ADM708R/

ADM708S/

ADM708T

TOP VIEW

GND

PFI

PFO

(Not to Scale)

NC = NO CONNECT

Figure 5. ADM708R/ADM708S/ADM708T

Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T

Pin No.

Mnemonic Description

Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS

logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds

the input high when floating.

V_CC

GND

PFI

Power Supply Input.

Ground. Ground reference for all signals (0 V).

Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.25 V, PFO

goes low. If unused, PFI should be connected to V_CC. If unused, PFI should be connected to V_CC.

Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is less than 1.25 V.

PFO

RESET

No Connect.

Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by V_CCbeing below the reset

threshold or by a low signal on the MR input. RESET remains low whenever V_CCis below the reset threshold. It

remains low for 200 ms after V_CCgoes above the reset threshold or MR goes from low to high. A watchdog

timeout does not trigger RESET unless WDO is connected to MR.

RESET

Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the

inverse of RESET.

Rev. D | Page 7 of 16

1...4 5 678 9 10...16

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