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ADM706PARZ-REEL

更新时间： 2024-02-29 08:54:35
品牌 Logo 应用领域
亚德诺 - ADI 电源电路电源管理电路微处理器光电二极管监控输入元件
页数 文件大小 规格书
16页 333K
描述
3 V, Voltage Monitoring Microprocessor Supervisory Circuits

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ADM706PARZ-REEL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：ROHS COMPLIANT, MS-012AA, SOIC-8针数：8
Reach Compliance Code：unknown风险等级：5.15
Is Samacsys：N其他特性：RESET THRESHOLD VOLTAGE IS 3.08V; MANUAL RESET INPUT
可调阈值：NO模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
信道数量：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
座面最大高度：1.75 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：3.9 mm
Base Number Matches：1

ADM706PARZ-REEL 数据手册

 浏览型号ADM706PARZ-REEL的Datasheet PDF文件第3页浏览型号ADM706PARZ-REEL的Datasheet PDF文件第4页浏览型号ADM706PARZ-REEL的Datasheet PDF文件第5页浏览型号ADM706PARZ-REEL的Datasheet PDF文件第7页浏览型号ADM706PARZ-REEL的Datasheet PDF文件第8页浏览型号ADM706PARZ-REEL的Datasheet PDF文件第9页 
ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
MR  
1
2
3
4
8
7
6
5
WDO  
RESET  
WDI  
MR  
1
2
3
4
8
7
6
5
WDO  
ADM706R/  
ADM706S/  
V
ADM706P  
V
RESET  
CC  
CC  
ADM706T  
TOP VIEW  
(Not to Scale)  
GND  
GND  
WDI  
PFO  
TOP VIEW  
(Not to Scale)  
PFI  
PFI  
PFO  
Figure 3. ADM706P  
Figure 4. ADM706R/ADM706S/ADM706T  
Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T  
Pin No.  
Mnemonic Description  
1
MR  
Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven  
from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An  
internal 70 μA pull-up current holds the input high when floating.  
2
3
4
VCC  
GND  
PFI  
Power Supply Input.  
Ground. Ground reference for all signals (0 V).  
Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less  
than 1.25 V, PFO goes low. If unused, PFI should be connected to GND.  
5
6
PFO  
WDI  
Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is  
less than 1.25 V.  
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout  
period, the watchdog output, WDO, goes low. The timer resets with each transition at the WDI  
input. Either a high-to-low or a low-to-high transition clears the counter. The internal timer is  
also cleared whenever reset is asserted.  
7 (ADM706R/ADM706S/  
ADM706T Only)  
RESET  
Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being  
below the reset threshold or by a low signal on the MR input. RESET remains low whenever VCC  
is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold  
or MR goes from low to high. A watchdog timeout does not trigger RESET unless WDO is  
connected to MR.  
7 (ADM706P Only)  
8
RESET  
WDO  
Logic Output. RESET is an active high output suitable for systems that use active high reset  
logic. It is the inverse of RESET.  
Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of  
inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO also goes  
low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As  
soon as VCC goes above the reset threshold, WDO goes high immediately.  
Rev. C | Page 6 of 16  
 
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