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ADM1068ACP-REEL7 PDF预览

ADM1068ACP-REEL7

更新时间： 2024-01-27 08:18:03
品牌 Logo 应用领域
亚德诺 - ADI 监控
页数 文件大小 规格书
28页 779K
描述
Super Sequencer⑩ and Monitor

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ADM1068ACP-REEL7 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
Reach Compliance Code：unknown风险等级：5.92
JESD-30 代码：S-PQFP-G32端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP32,.35SQ,32封装形状：SQUARE
封装形式：FLATPACK电源：3/5 V
认证状态：Not Qualified子类别：Power Management Circuits
最大供电电流 (Isup)：6 mA表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
Base Number Matches：1

ADM1068ACP-REEL7 数据手册

 浏览型号ADM1068ACP-REEL7的Datasheet PDF文件第3页浏览型号ADM1068ACP-REEL7的Datasheet PDF文件第4页浏览型号ADM1068ACP-REEL7的Datasheet PDF文件第5页浏览型号ADM1068ACP-REEL7的Datasheet PDF文件第7页浏览型号ADM1068ACP-REEL7的Datasheet PDF文件第8页浏览型号ADM1068ACP-REEL7的Datasheet PDF文件第9页 
ADM1068  
Preliminary Technical Data  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
25  
32  
1
24  
VX1  
VX2  
VX3  
VX4  
VP1  
VP2  
VP3  
VH  
PDO1  
PDO2  
PDO3  
PDO4  
PDO5  
PDO6  
PDO7  
PDO8  
PIN 1  
INDICATOR  
ADM1068  
TOP VIEW  
(Not to Scale)  
8
17  
9
16  
NC = NO CONNECT  
Figure 3. LQFP Pin Configuration  
Table 2. Pin Function Descriptions  
Pin No.  
11, 13-16  
1–4  
Mnemonic  
Description  
NC  
VX1–4  
No connection.  
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.  
Alternatively, these pins can be used as general-purpose digital inputs.  
5–7  
8
VP1–3  
VH  
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation  
on a potential divider connected to these pins, the output of which connects to a supply fault detector. These  
pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.  
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation  
on a potential divider connected to this pin, the output of which connects to a supply fault detector. This pin  
allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.  
9
AGND  
REFGND  
REFOUT  
PDO8–1  
PDOGND  
VCCP  
A0  
A1  
SCL  
SDA  
Ground Return for Input Attenuators.  
Ground Return for On-Chip Reference Circuits.  
2.048 V Reference Output.  
Programmable Output Drivers.  
10  
12  
17-24  
25  
26  
27  
28  
29  
30  
31  
32  
Ground Return for Output Drivers.  
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin and GND.  
Logic Input. This pin sets the seventh bit of the SMBus interface address.  
Logic Input. This pin sets the sixth bit of the SMBus interface address.  
SMBus Clock Pin. Open-drain output requires external resistive pull-up.  
SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.  
Device Supply Voltage. Linearly regulated from the highest of the VP1–3, VH pins to a typical of 4.75 V.  
Supply Ground.  
VDDCAP  
GND  
Rev. PrB | Page 6 of 28  
 
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