ADM1066
Parameter
Min
Typ
0.44
84
Max
Unit
ms
ms
Test Conditions/Comments
Conversion Time
One conversion on one channel
All 12 channels selected, 16x averaging enabled
VREFIN = 2.048 V
Offset Error
2
LSB
Input Noise
0.25
8
LSBrms Direct input (no attenuator)
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Bits
Code 0x80 Output Voltage
6 DACs are individually selectable for centering on
one of four output voltage ranges
Range 1
Range 2
Range 3
0.592
0.796
0.996
1.246
0.6
0.8
1
1.25
601.25
2.36
0.603
0.803
1.003
1.253
V
V
V
V
mV
mV
LSB
LSB
%
mV
mV
pF
µs
Range 4
Output Voltage Range
LSB Step Size
INL
DNL
Gain Error
Load Regulation
Same range, independent of center point
Endpoint corrected
0.75
0.4
1
-4
2
Sourcing Current, IREFOUTMA X= -200µA
Sinking Current, IREFOUTMA X= 100µA
Maximum Load Capacitance
Settling Time into 50 pF Load
Load Regulation
50
2
2.5
60
40
mV
dB
dB
Per mA
DC
PSRR
100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
2.043
1
2.048
−0.25
0.25
2.053
V
No load
mV
mV
µF
mV
dB
Sourcing current, IDACnMAX = −100 µA
Sinking current, IDACnMAX = 100 µA
Capacitor required for decoupling, stability
Per 100 µA
Minimum Load Capacitance
Load Regulation
PSRR
2
60
DC
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode (PDO1–6)
Output Impedance
500
12.5
12
kΩ
V
V
VOH
11
10.5
14
13.5
IOH = 0
IOH = 1µA
2 V < VOH < 7 V
IOUTAVG
20
µA
Standard (Digital Output) Mode (PDO1–10)
VOH
2.4
V
V
V
V
mA
mA
kΩ
mA
VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA
VPU to Vpn = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
4.5
VPU − 0.3
0
VOL
0.50
20
60
IOL = 20 mA
2
IOL
Maximum sink current per PDO pin
Maximum total sink for all PDOs
Internal pull-up
Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
2
ISINK
RPULL-UP
ISOURCE (VPn)2
20
2
Three-State Output Leakage Current
Oscillator Frequency
10
110
µA
kHz
VPDO = 14.4 V
All on-chip time delays derived from this clock
90
100
Rev. 0 | Page 5 of 32