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ADM1067ACPZ

更新时间： 2024-01-30 12:48:59
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 510K
描述
Super Sequencer® with Open-Loop Margining DACs

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ADM1067ACPZ 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC40,.24SQ,20针数：40
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.8
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：S-XQCC-N40JESD-609代码：e3
长度：6 mm湿度敏感等级：3
信道数量：10功能数量：1
端子数量：40最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC40,.24SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：4.75 V
认证状态：Not Qualified座面最大高度：1 mm
子类别：Power Management Circuits标称供电电压 (Vsup)：4.75 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：6 mm
Base Number Matches：1

ADM1067ACPZ 数据手册

 浏览型号ADM1067ACPZ的Datasheet PDF文件第2页浏览型号ADM1067ACPZ的Datasheet PDF文件第3页浏览型号ADM1067ACPZ的Datasheet PDF文件第4页浏览型号ADM1067ACPZ的Datasheet PDF文件第5页浏览型号ADM1067ACPZ的Datasheet PDF文件第6页浏览型号ADM1067ACPZ的Datasheet PDF文件第7页 
Super Sequencer with  
Open-Loop Margining DACs  
Data Sheet  
ADM1067  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
REFOUT REFGND SDA SCL A1  
A0  
Complete supervisory and sequencing solution for up to  
10 supplies  
SMBus  
INTERFACE  
ADM1067  
VREF  
EEPROM  
10 supply fault detectors enable supervision of supplies to  
<0.5% accuracy at all voltages at 25°C  
<1.0% accuracy across all voltages and temperatures  
5 selectable input attenuators allow supervision of supplies to  
14.4 V on VH  
VX1  
VX2  
VX3  
VX4  
VX5  
PDO1  
PDO2  
PDO3  
PDO4  
PDO5  
PDO6  
CONFIGURABLE  
OUTPUT  
DRIVERS  
DUAL-  
FUNCTION  
INPUTS  
(LOGIC INPUTS  
OR  
(HV CAPABLE OF  
DRIVING GATES  
OF N-FET)  
SFDs)  
6 V on VP1 to VP4 (VPx)  
SEQUENCING  
ENGINE  
5 dual-function inputs, VX1 to VX5 (VXx)  
High impedance input to supply fault detector with  
thresholds between 0.573 V and 1.375 V  
General-purpose logic input  
VP1  
VP2  
PDO7  
PDO8  
PDO9  
CONFIGURABLE  
OUTPUT  
PROGRAMMABLE  
RESET  
DRIVERS  
GENERATORS  
VP3  
(LV CAPABLE  
OF DRIVING  
LOGIC SIGNALS)  
(SFDs)  
VP4  
VH  
PDO10  
10 programmable driver outputs, PDO1 to PDO10 (PDOx)  
Open-collector with external pull-up  
Push/pull output, driven to VDDCAP or VPx  
Open collector with weak pull-up to VDDCAP or VPx  
Internally charge-pumped high drive for use with external  
N-FET (PDO1 to PDO6 only)  
PDOGND  
AGND  
GND  
VCCP  
MDN  
VDD  
VDDCAP  
MUP  
ARBITRATOR  
V
V
V
DAC  
V
DAC  
V
DAC  
V
OUT  
DAC  
OUT  
DAC  
OUT  
OUT  
OUT  
OUT  
DAC  
Sequencing engine (SE) implements state machine control of  
PDO outputs  
DAC1  
DAC2  
DAC3  
DAC4  
DAC5  
DAC6  
Figure 1.  
State changes conditional on input events  
Enables complex control of boards  
GENERAL DESCRIPTION  
Power-up and power-down sequence control  
Fault event handling  
Interrupt generation on warnings  
The ADM1067 Super Sequencer® is a configurable supervisory/  
sequencing device that offers a single-chip solution for supply  
monitoring and sequencing in multiple supply systems. In addition  
to these functions, the ADM1067 integrates six 8-bit voltage  
output DACs. These circuits can be used to implement an open-  
loop margining system that enables supply adjustment by altering  
either the feedback node or reference of a dc-to-dc converter  
using the DAC outputs.  
Watchdog function can be integrated in SE  
Program software control of sequencing through SMBus  
Open-loop margining solution for 6 voltage rails  
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage  
adjustment via dc-to-dc converter trim/feedback node  
Device powered by the highest of VPx, VH for improved  
redundancy  
For more information about the ADM1067 register map, refer  
to the AN-698 Application Note.  
User EEPROM: 256 bytes  
Industry-standard 2-wire bus interface (SMBus)  
Guaranteed PDO low with VH, VPx = 1.2 V  
Available in 40-lead, 6 mm × 6 mm LFCSP and  
48-lead, 7 mm × 7 mm TQFP packages  
APPLICATIONS  
Central office systems  
Servers/routers  
Multivoltage system line cards  
DSP/FPGA supply sequencing  
In-circuit testing of margined supplies  
Rev. E  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2004–2015 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 
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