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ADM1025ARQ-REEL

更新时间： 2024-01-29 11:56:37

品牌	Logo	应用领域
安森美 - ONSEMI		电源电路电源管理电路光电二极管监控输入元件 PC
页数	文件大小	规格书
21页	297K
描述
Low Cost PC Hardware Monitor ASIC

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ADM1025ARQ-REEL 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	0.025 INCH PITCH, SOIC, QSOP-16	针数：	16
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.12
Is Samacsys：	N	其他特性：	PROGRAMMABLE ANALOG/DIGITAL INPUTS
可调阈值：	NO	模拟集成电路 - 其他类型：	POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	4.9 mm	湿度敏感等级：	1
信道数量：	6	功能数量：	1
端子数量：	16	最高工作温度：	100 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.75 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	3.9 mm	Base Number Matches：	1

ADM1025ARQ-REEL 数据手册

ADM1025/ADM1025A

Preliminary Technical Data

If ADD is left open-circuit, the default address will be 0101110.

ADD is sampled only after power-up, so any changes made will

have no effect, unless power is cycled.

transmitted over the serial bus in a single READ or

WRITE operation is limited only by what the master and

slave devices can handle.

The facility to make hardwired changes to A1 and A0 allows the

user to avoid conflicts with other devices sharing the same

serial bus if, for example, more than one ADM1025/

ADM1025A is used in a system. However, as previously

mentioned, the ADD pin may also function as a reset output or

interrupt output. Use of these functions may restrict the

addresses that can be set. See the sections on RST and INT for

further information.

When all data bytes have been read or written, STOP

conditions are established. In WRITE mode, the master will

pull the data line high during the 10th clock pulse to assert a

STOP condition. In READ mode, the master device will

override the Acknowledge Bit by pulling the data line high

during the low period before the 9th clock pulse. This is

known as No Acknowledge. The master will then take the

data line low during the low period before the 10th clock

pulse, then high during the 10th clock pulse to assert a STOP

condition.

The serial bus protocol operates as follows.

1) The master initiates data transfer by establishing a START

condition, defined as a high-to-low transition on the serial

data line SDA while the serial clock line SCL remains high.

This indicates that an address/data stream will follow. All

slave peripherals connected to the serial bus respond to the

START condition and shift in the next eight bits, consisting

of a 7-bit address (MSB first) plus an R/W bit, which

determines the direction of the data transfer, i.e., whether

data will be written to or read from the slave device.

Any number of bytes of data may be transferred over the serial

bus in one operation, but it is not possible to mix read and write

in one operation because the type of operation is determined at

the beginning and cannot subsequently be changed without

starting a new operation.

In the case of the ADM1025/ADM1025A, write operations

contain either one or two bytes, and read operations contain

one byte and perform the following functions.

To write data to one of the device data registers or read data

from it, the Address Pointer Register must be set so that the

correct data register is addressed; data can then be written into

that register or read from it. The first byte of a write operation

always contains an address that is stored in the Address Pointer

operation contains a second data byte that is written to the

The peripheral whose address corresponds to the

transmitted address responds by pulling the data line low

during the low period before the ninth clock pulse, known

as the Acknowledge Bit. All other devices on the bus now

remain idle while the selected device waits for data to be

read from or written to it. If the R/W bit is a 0, the master

will write to the slave device. If the R/W bit is a 1, the

master will read from the slave device.

This is illustrated in Figure 11. The device address is sent over

the bus followed by R/W set to 0. This is followed by two data

bytes. The first data byte is the address of the internal data

internal data register.

2) Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an Acknowledge Bit

from the slave device. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, since a low-to-high

transition when the clock is high may be interpreted as a

STOP signal. The number of data bytes that can be

Figure 11. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

Rev. P5 | Page 10 of 21| www.onsemi.com

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