ADL5541

更新时间： 2024-02-24 02:10:48

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	285K
描述
50 MHz to 6 GHz RF/IF Gain Block

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中文翻译

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技术参数
数据手册

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ADL5541 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.33.00.01
风险等级：	5.7	Is Samacsys：	N
特性阻抗：	50 Ω	构造：	COMPONENT
增益：	14.3 dB	最大输入功率 (CW)：	10 dBm
JESD-609代码：	e3	最大工作频率：	6000 MHz
最小工作频率：	50 MHz	最高工作温度：	85 °C
最低工作温度：	-40 °C	射频/微波设备类型：	WIDE BAND MEDIUM POWER
端子面层：	Matte Tin (Sn)	Base Number Matches：	1

ADL5541 数据手册

ADL5541

BASIC CONNECTIONS

4.5

4.0

3.5

3.0

2.5

2.0

The basic connections for operating the ADL5541 are shown in

Figure 13. Recommended components are listed in Table 5. The

input and output should be ac-coupled with appropriately sized

capacitors (device characterization was performed with 33 pF

capacitors). A 5 V dc bias is supplied to the amplifier via GND

(Pin 6) and through a biasing inductor connected to RFOUT

(Pin 8). The bias voltage should be decoupled using a 1 μF

capacitor, a 1.2 nF capacitor, and two 68 pF capacitors.

VCC

1µF

1.2nF

68pF

47nH

ADL5541

33pF

100

150

200

250

300

350

400

450

500

RFIN

1 RFIN RFOUT 8

RFOUT

FREQUENCY (MHz)

2 GND

3 GND

4 CB

GND 7

GND 6

GND

Figure 15. Noise Figure vs. Frequency from 50 MHz to 500 MHz

VPOS 5

VCC

SOLDERING INFORMATION AND RECOMMENDED

PCB LAND PATTERN

1µF

68pF

Figure 16 shows the recommended land pattern for the ADL5541.

To minimize thermal impedance, the exposed paddle on the

package underside should be soldered down to a ground plane

along with Pin 2, Pin 3, Pin 6, and Pin 7. If multiple ground

layers exist, they should be stitched together using vias (a

minimum of five vias is recommended). For more information

on land pattern design and layout, refer to Application Note

AN-772, A Design and Manufacturing Guide for the Lead Frame

Chip Scale Package (LFCSP).

Figure 13. Basic Connections

For operation between 50 MHz and 500 MHz, a larger biasing

choke and ac coupling capacitors are necessary (see Table 5).

Figure 14 shows a plot of the input return loss, the output

return loss and the gain with these components. At 100 MHz,

the ADL5541 achieves an OIP3 of 38 dBm (P_OUT= 0 dBm per

tone). The noise figure performance for operation from 50

MHz to 500 MHz is shown in Figure 15. When operating below

50 MHz, the ADL5541 exhibits gain peaking, and the input and

output match degrade significantly.

2.03mm

PIN 1

PIN 8

17.0

16.5

16.0

15.5

15.0

14.5

14.0

13.5

13.0

12.5

12.0

–5

–10

–15

–20

–25

–30

0.5mm

1.85mm

1.78mm

S21

PIN 4

PIN 5

1.53mm

S22

0.71mm

Figure 16. Recommended Land Pattern

S11

100

150

200

250

300

350

400

450

500

FREQUENCY (MHz)

Figure 14. Input Return Loss (S11), Output Return Loss (S22), and

Gain (S21) vs. Frequency

Table 5. Recommended Components for Basic Connections

Frequency

50 MHz to 500 MHz

500 MHz to 6000 MHz

0.1 μF 0.1 μF 1 μF 470 nH (Coilcraft 0603LS-471-NX or equivalent)

68 pF 1.2 nF 1 μF 68 pF

33 pF

1 μF 47 nH (Coilcraft 0603CS-47-NX or equivalent)

Rev. 0 | Page 10 of 12

1...7 8 91011 12

中文翻译

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ADL5544ARKZ	ADI	获取价格	30 MHz to 6 GHz RF/IF Gain Block
ADL5544ARKZ-R7	ADI	获取价格	30 MHz to 6 GHz RF/IF Gain Block
ADL5544-EVALZ	ADI	获取价格	30 MHz to 6 GHz RF/IF Gain Block

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