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ADG467BR PDF预览

ADG467BR

更新时间: 2024-01-19 01:06:25
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
10页 235K
描述
Triple and Octal Channel Protectors

ADG467BR 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOT
包装说明:SMALL OUTLINE, R-PDSO-G18针数:18
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.11
最大漏极电流 (ID):0.02 A最大漏源导通电阻:95 Ω
FET 技术:METAL-OXIDE SEMICONDUCTORJESD-30 代码:R-PDSO-G18
JESD-609代码:e3湿度敏感等级:3
端子数量:18工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260极性/信道类型:N-CHANNEL
认证状态:Not Qualified表面贴装:YES
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:30
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

ADG467BR 数据手册

 浏览型号ADG467BR的Datasheet PDF文件第2页浏览型号ADG467BR的Datasheet PDF文件第3页浏览型号ADG467BR的Datasheet PDF文件第4页浏览型号ADG467BR的Datasheet PDF文件第5页浏览型号ADG467BR的Datasheet PDF文件第6页浏览型号ADG467BR的Datasheet PDF文件第7页 
Triple and Octal  
a
Channel Protectors  
ADG466/ADG467  
FEATURES  
FUNCTIONAL BLOCK DIAGRAMS  
Fault and Overvoltage Protection up to ؎40 V  
Signal Paths Open Circuit with Power Off  
Signal Path Resistance of RON with Power On  
44 V Supply Maximum Ratings  
Low On Resistance  
ADG466/ADG467 60 typ  
1 nA Max Path Current Leakage @ +25؇C  
Low RON Match (5 max)  
V
V
V
V
SS  
DD  
SS  
DD  
V
V
V
V
V
V
V
V
V
V
V
S1  
S2  
S3  
D1  
D2  
D3  
S1  
D1  
D2  
D3  
S2  
V
S3  
ADG466  
Low Power Dissipation 0.8 W typ  
Latch-Up Proof Construction  
V
V
D8  
S8  
V
APPLICATIONS  
ATE Equipment  
VIN  
OUT  
V
IN  
ADG467  
V
OUT  
Sensitive Measurement Equipment  
Hot-Insertion Rack Systems  
V
DD  
V
DD  
OUTPUT CLAMPED  
GENERAL DESCRIPTION  
@ V – 1.5V  
DD  
The ADG466 and ADG467 are triple and octal channel pro-  
tectors, respectively. The channel protector is placed in series  
with the signal path. The channel protector will protect sensitive  
components from voltage transience in the signal path whether  
the power supplies are present or not. Because the channel  
protection works whether the supplies are present or not, the  
channel protectors are ideal for use in applications where  
correct power sequencing can’t always be guaranteed (e.g., hot-  
insertion rack systems) to protect analog inputs. This is dis-  
cussed further, and some example circuits are given in the  
Applications section of this data sheet.  
ADG467 is 60 typ with a leakage current of ±1 nA max.  
When power is disconnected, the input leakage current is ap-  
proximately ±5 nA typ.  
The ADG466 is available in 8-lead DIP, SOIC and µSOIC  
packages. The ADG467 is available in an 18-lead SOIC package  
and a 20-lead SSOP package.  
Each channel protector has an independent operation and con-  
sists of an n-channel MOSFET, a p-channel MOSFET and an  
n-channel MOSFET, connected in series. The channel protec-  
tor behaves just like a series resistor during normal operation,  
i.e., (VSS + 2 V) < VIN < (VDD – 1.5 V). When a channel’s ana-  
PRODUCT HIGHLIGHTS  
1. Fault Protection.  
The ADG466 and ADG467 can withstand continuous volt-  
age inputs from –40 V to +40 V. When a fault occurs due to  
the power supplies being turned off or due to an overvoltage  
being applied to the ADG466 and ADG467, the output is  
clamped. When power is turned off, current is limited to the  
microampere level.  
log input exceeds the power supplies (including VDD and VSS  
=
0 V), one of the MOSFETs will switch off, clamping the output  
to either VSS + 2 V or VDD – 1.5 V. Circuitry and signal source  
protection is provided in the event of an overvoltage or power  
loss. The channel protectors can withstand overvoltage inputs  
from –40 V to +40 V. See the Circuit Information section of  
this data sheet.  
2. Low Power Dissipation.  
3. Low RON  
.
ADG466/ADG467 60 typ.  
The ADG466 and ADG467 can operate off both bipolar and  
unipolar supplies. The channels are normally on when power is  
connected and open circuit when power is disconnected. With  
power supplies of ±15 V, the on-resistance of the ADG466 and  
4. Trench Isolation Latch-Up Proof Construction.  
A dielectric trench separates the p- and n-channel MOSFETs  
thereby preventing latch-up.  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 1998  

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