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ADG3308BCBZ-1-REEL PDF预览

ADG3308BCBZ-1-REEL

更新时间: 2024-02-23 13:44:29
品牌 Logo 应用领域
亚德诺 - ADI 转换器电平转换器驱动程序和接口接口集成电路
页数 文件大小 规格书
20页 622K
描述
Low Voltage, 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translators

ADG3308BCBZ-1-REEL 技术参数

是否无铅: 含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:VFBGA, BGA20,4X5,20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.13
接口集成电路类型:INTERFACE CIRCUITJESD-30 代码:R-PBGA-B20
JESD-609代码:e1长度:2.5 mm
湿度敏感等级:1功能数量:1
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA20,4X5,20
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.2/5,1.8/5 V
认证状态:Not Qualified座面最大高度:0.65 mm
子类别:Other Interface ICs最大供电电压:5.5 V
最小供电电压:1.15 V标称供电电压:1.8 V
电源电压1-最大:5.5 V电源电压1-分钟:1.65 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:2 mm
Base Number Matches:1

ADG3308BCBZ-1-REEL 数据手册

 浏览型号ADG3308BCBZ-1-REEL的Datasheet PDF文件第13页浏览型号ADG3308BCBZ-1-REEL的Datasheet PDF文件第14页浏览型号ADG3308BCBZ-1-REEL的Datasheet PDF文件第15页浏览型号ADG3308BCBZ-1-REEL的Datasheet PDF文件第17页浏览型号ADG3308BCBZ-1-REEL的Datasheet PDF文件第18页浏览型号ADG3308BCBZ-1-REEL的Datasheet PDF文件第19页 
ADG3308/ADG3308-1  
THEORY OF OPERATION  
The ADG3308/ADG3308-1/ADG3308-2 level translators allow  
the level shifting necessary for data transfer in a system where  
multiple supply voltages are used. The device requires two  
supplies, VCCA and VCCY (VCCA ≤ VCCY). These supplies set the  
logic levels on each side of the device. When driving the A pins,  
the device translates the VCCA compatible logic levels to VCCY  
compatible logic levels available at the Y pins. Similarly, because  
the device is capable of bidirectional translation, when driving  
the Y pins the VCCY compatible logic levels are translated to the  
VCCA compatible logic levels available at the A pins. When  
EN = 0, the A1 pin to the A8 pin and the Y1 pin to the Y8 pin  
are three-stated. When EN is driven high, the ADG3308/  
ADG3308-1/ADG3308-2 go into normal operation mode and  
perform level translation.  
INPUT DRIVING REQUIREMENTS  
To ensure correct operation of the ADG3308/ADG3308-1/  
ADG3308-2, the circuit that drives the input of the device  
should be able to ensure rise/fall times of less than 3 ns when  
driving a load consisting of a 6 kΩ resistor in parallel with the  
input capacitance of the ADG3308/ADG3308-1/ADG3308-2  
channel.  
OUTPUT LOAD REQUIREMENTS  
The ADG3308/ADG3308-1/ADG3308-2 level translators are  
designed to drive CMOS-compatible loads. If current-driving  
capability is required, it is recommended to use buffers between  
the ADG3308/ADG3308-1/ADG3308-2 outputs and the load.  
ENABLE OPERATION  
LEVEL TRANSLATOR ARCHITECTURE  
The ADG3308/ADG3308-1/ADG3308-2 provide three-state  
operation at the A I/O pins and the Y I/O pins by using the  
enable (EN) pin, as shown in Table 4.  
The ADG3308/ADG3308-1/ADG3308-2 consist of eight  
bidirectional channels. Each channel can translate logic levels  
in either the A→Y or the Y→A direction. They use a one-shot  
accelerator architecture, ensuring excellent switching charac-  
teristics. Figure 39 shows a simplified block diagram of a  
bidirectional channel.  
Table 4. Truth Table  
EN  
Y I/O Pins  
A I/O Pins  
0
1
High-Z1  
High-Z1  
Normal operation2  
Normal operation2  
V
V
CCA  
CCY  
1 High impedance state.  
2 In normal operation, the ADG3308/ADG3308-1/ADG3308-2 perform level  
translation.  
T1  
T2  
6k  
When EN = 0, the ADG3308/ADG3308-1/ADG3308-2 enter  
into three-state mode. In this mode, the current consumption  
from both the VCCA and VCCY supplies is reduced, allowing the  
user to save power, which is critical, especially in battery-  
operated systems. The EN input pin can only be driven with  
U1  
U2  
P
Y
A
ONE-SHOT GENERATOR  
N
V
CCY compatible logic levels for the ADG3308, whereas the  
ADG3308-1/ADG3308-2 can be driven with either VCCA- or  
CCY compatible logic levels.  
U4  
U3  
6kΩ  
V
POWER SUPPLIES  
T4  
T3  
For proper operation of the device, the voltage applied to the  
VCCA must always be less than or equal to the voltage applied  
to VCCY. To meet this condition, the recommended power-up  
sequence is VCCY first and then VCCA. The ADG3308/ADG3308-1/  
ADG3308-2 operate properly only after both supply voltages  
reach their nominal values. It is not recommended to use the part  
in a system where, during power-up, VCCA may be greater than  
Figure 39. Simplified Block Diagram of an  
ADG3308/ADG3308-1/ADG3308-2 Channel  
The logic level translation in the A→Y direction is performed  
using a level translator (U1) and an inverter (U2), whereas the  
translation in the Y→A direction is performed using the U3  
inverter and U4 inverter. The one-shot generator detects a rising  
or falling edge present on either the A side or the Y side of the  
channel. It sends a short pulse that turns on the PMOS transistors  
(T1 and T2) for a rising edge, or the NMOS transistors (T3 and  
T4) for a falling edge. This charges/discharges the capacitive load  
faster, resulting in fast rise and fall times.  
V
V
CCY due to a significant increase in the current taken from the  
CCA supply. For optimum performance, the VCCA and VCCY pins  
should be decoupled to GND as close as possible to the device.  
The inputs of the unused channels (A or Y) should be tied to  
their corresponding VCC rail (VCCA or VCCY) or to GND.  
Rev. C | Page 16 of 20  
 
 
 

ADG3308BCBZ-1-REEL 替代型号

型号 品牌 替代类型 描述 数据表
ADG3308BCBZ-1-RL7 ADI

完全替代

Low Voltage, 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translators

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