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ADF9010BCPZ-RL

更新时间： 2024-02-02 10:08:12
品牌 Logo 应用领域
亚德诺 - ADI ISM频段
页数 文件大小 规格书
28页 476K
描述
900 MHz ISM Band Analog RF Front End

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中文翻译

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ADF9010BCPZ-RL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC48,.27SQ,20针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.66
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：7 mm湿度敏感等级：3
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC48,.27SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1 mm子类别：Other Telecom ICs
最大压摆率：0.41 mA标称供电电压：3.3 V
表面贴装：YES技术：BICMOS
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：7 mm
Base Number Matches：1

ADF9010BCPZ-RL 数据手册

 浏览型号ADF9010BCPZ-RL的Datasheet PDF文件第5页浏览型号ADF9010BCPZ-RL的Datasheet PDF文件第6页浏览型号ADF9010BCPZ-RL的Datasheet PDF文件第7页浏览型号ADF9010BCPZ-RL的Datasheet PDF文件第9页浏览型号ADF9010BCPZ-RL的Datasheet PDF文件第10页浏览型号ADF9010BCPZ-RL的Datasheet PDF文件第11页 
ADF9010  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
Rx IP  
IN  
1
2
36 Rx IN  
BB  
PIN 1  
INDICATOR  
Rx IN  
IN  
35 Rx IP  
BB  
34 Rx QP  
BB  
RxV  
DD  
3
33 Rx QN  
BB  
LO  
OUT  
N
4
LO  
OUT  
P
5
32 C  
31 C  
30 R  
3
4
EXT  
EXT  
SET  
AGND  
DGND  
6
ADF9010  
TOP VIEW  
7
(Not to Scale)  
REF  
IN  
8
29 AV  
DD  
DV  
9
28 Tx IN  
DD  
BB  
27 Tx IP  
V
10  
P
BB  
CP 11  
26 Tx QP  
BB  
25 Tx QN  
AGND 12  
BB  
NC = NO CONNECT  
Figure 3. Pin Configuration  
Table 6. Pin Function Descriptions  
Pin No.  
Mnemonic  
RxINIP, RxININ  
RxVDD  
Description  
1, 2  
3, 46  
Input/Complementary In-Phase Input to the Receive Filter Stage.  
Receiver Filter Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the  
analog ground plane should be placed as close as possible to this pin. RxVDD must be the same  
value as AVDD and DVDD  
.
4, 5  
LOOUTN, LOOUT  
P
Buffered Local Oscillator Output. These outputs are used to provide the LO for the external RF  
demodulator. These require an RF choke to AVDD and a dc bypass capacitor before connection to a  
demodulator.  
6, 12, 18, 24, 44 AGND  
Analog Ground. This is the ground return path of analog circuitry.  
Digital Ground.  
PLL Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent  
input resistance of 100 kΩ (see Figure 13). This input can be driven from a TTL or CMOS crystal  
oscillator, or it should be ac-coupled.  
7
8
DGND  
REFIN  
9, 37  
10  
DVDD  
VP  
Digital Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the digital  
ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD  
.
This pin supplies the voltage to the charge pump. If the internal VCO is used, it should equal AVDD  
and DVDD. If an external VCO is used, the voltage can be AVDD < VP < 5.5 V.  
11  
CP  
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter, which in turn  
drives the external VCO.  
13  
CT  
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to  
AGND with a value of 10 nF. The output voltage on this part is proportional to temperature. At  
ambient temperature, the voltage is 2.0 V.  
14  
CEXT  
CEXT  
1
2
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to  
AGND with a value of 10 nF.  
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to  
AGND with a value of 10 nF.  
15  
16, 21, 29  
AVDD  
Analog Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the  
analog ground plane should be placed as close as possible to this pin. AVDD must be the same value  
as DVDD  
.
Rev. 0 | Page 8 of 28  
 
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中文翻译

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