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ADF9010BCPZ-RL

更新时间： 2024-02-08 09:28:12

品牌	Logo	应用领域
亚德诺 - ADI		ISM频段
页数	文件大小	规格书
28页	476K
描述
900 MHz ISM Band Analog RF Front End

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技术参数
数据手册

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ADF9010BCPZ-RL 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN, LCC48,.27SQ,20	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.66
JESD-30 代码：	S-XQCC-N48	JESD-609代码：	e3
长度：	7 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC48,.27SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	Other Telecom ICs
最大压摆率：	0.41 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BICMOS
电信集成电路类型：	TELECOM CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	7 mm
Base Number Matches：	1

ADF9010BCPZ-RL 数据手册

ADF9010

Rx Calibration Divider

A Counter Latch

Bit RC6 to Bit RC1 program a 6-bit divider, which outputs

a divided REF_INsignal to assist calibration of the cutoff

frequency, f_C, of the Rx filters. The calibration circuit uses

this divideddown PLL reference frequency to ensure an

accurate cutoff frequency in the Rx filter. The divider value

should be chosen to ensure that the frequency of the divided

down signal is exactly 2 MHz, that is, if a 32 MHz crystal is

used as the PLL REF_INfrequency, then a value of 16 should

be programmed to the counter to ensure accurate calibration.

Bit A5 to Bit A1 program the 5-bit A counter. The divide range

is 0 (00000) to 31 (11111).

Rx LATCH

Program the Rx latch with (C2, C1) = (1, 1). Figure 26 shows

the input data format for programming the LO latch.

High-Pass Filter Boost

This function is enabled by setting the HP bit to 1. A 0 disables

this function. This is used to reduce settling time on the high-

pass filter from the Rx demodulator. This is usually used in

conjunction with the high-pass filter boost counter (See the

Rx Calibration Latch section).

High-Pass Filter Boost Timeout Counter

In most applications of the ADF9010, a high-pass filter is placed

between the demodulator outputs and the ADF9010 Rx inputs.

The capacitors used in these filters may require a long charge

up time, and to address this, a filter boost function exists that

charges up the capacitor to ~1.6 V. The duration for this boost

is set by the product of the period of the Rx calibration signal,

(REF_INdivided by the Rx calibration divider) and the 6-bit value

programmed to these registers. This value can be as large as 63.

Programming a value of 000000 leads to the calibration time

being manually set by the HPF boost in the Rx latch. It becomes

necessary in such cases to program this bit to 0 for normal Rx

operation.

Rx Filter Bandwidth

The Rx filter bandwidth is programmable and is controlled by

Bit BW2 and Bit BW1. See the truth table in Figure 26.

Rx Filter Gain Steps

Bit G3 to Bit G1 set the gain of the Rx filters. The gain can

vary from 3 dB to 24 dB in 3 dB steps. See the truth table in

Figure 26.

INITIALIZATION

The correct initialization sequence for the ADF9010 is as follows:

LO LATCH

1. Power-down all blocks: Tx, Rx, PLL, and VCO. Set the Tx

output power off control latch to (1, 1). Set the LO phase

select off (P1, P2, P3) in Tx latch to (1, 1, 1).

2. Program the R1 latch with the desired R counter and

Tx values.

Program the LO latch with (C2, C1) = (1, 0). Figure 25 shows

the input data format for programming the LO latch.

Prescaler

Bit P2 and Bit P1 in the LO latch set the prescaler values.

3. Program R5 with Rx calibration data for frequency

calibration and high-pass filter boost.

CP Gain

4. Program R0 to power up all LO and Tx/Rx blocks.

5. Program R2 to encode correct LO frequency.

6. Program R3 to power up Rx filter.

Setting G1 to 0 chooses the programmed charge pump current

setting from the control latch. Setting this bit to 1 chooses the

maximum possible setting.

N Div Mux

INTERFACING

The ADF9010 has a simple SPI®-compatible interface for

writing to the device. S_CLK, S_DATA, and S_LEcontrol the data

transfer. See Figure 2 for the timing diagram.

Setting M1 to 0 feeds the VCO signals back to the N divider.

Setting this bit to 1 allows the mux signal to be fed back instead.

B Counter Latch

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible for the device

is 833 kHz or one update every 1.2 μs. This is certainly more

than adequate for systems that have typical lock times in

hundreds of microseconds.

Bit B13 to Bit B1 program the B counter. The divide range is

3 (00 … 0011) to 8191 (11 … 111).

Rev. 0 | Page 22 of 28

1...19 20 212223 24 25...28

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ADF9010BCPZ-RL7	ADI	900 MHz ISM Band Analog RF Front End	获取价格
ADFC13	ABRACON	MULTI-LAYER DIELECTRIC FILTER	获取价格
ADFC13-1906.50-A	ABRACON	Dielectric BPF, 1906.5MHz	获取价格
ADFC13-1906.50-A-T	ABRACON	Dielectric BPF, 1906.5MHz	获取价格
ADFC13-1906.50-B	ABRACON	Dielectric BPF, 1906.5MHz	获取价格
ADFC13-1906.50-B-T	ABRACON	Dielectric BPF, 1906.5MHz	获取价格

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