PRELIMINARY TECHNICAL DATA
ADF4360-2
PIN DESCRIPTION
Mnemonic
Function
AVDD
Analog Power Supply. This may range from 3.0V to 3.6V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
DVDD
VVCO
RSET
Digital Power Supply. This may range from 3.0V to 3.6V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD
.
Power supply for the VCO. This may range from 3.0V to 3.6V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. VVCO must be the same value as AVDD.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for
the synthesizer. The nominal voltage potential at the RSET pin is 0.6V. The relationship between ICP
and RSET is
11.75
I
=
CPmax
R
SET
So, with RSET = 4.7kΩ, ICPmax = 2.5mA.
MUXOUT
CP
This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
Charge Pump Output. When enabled this provides ICP to the external loop filter, which in turn drives
the internal VCO.
VTUNE
Control input to the VCO. This voltage determines the output frequency and is derived from filtering
the CPOUT voltage.
CC
C N
Internal compensation node. This pin must be decoupled to ground with a 10nF capacitor.
Internal compensation node. This pin must be decoupled to VVCO with a 10uF capacitor.
RFOUTA
VCO output. The output level is programmable from -6dBm to -13dBm. See Page 18 for a description
of various output stages.
RFOUTB
VCO complementary output. The output level is programmable from -6dBm to -13dBm. See Page 18
for a description of various output stages.
CPGND
DGND
AGND
Charge Pump Ground. This is the ground return path for the charge pump.
Digital Ground.
Analog Ground. This is the ground return path of the prescaler & VCO.
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the relevant latch is selected using the control bits.
DATA
CLK
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three state
mode. Taking the pin high will power up the device depending on the status of the power-down bits.
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac coupled.
REV. PrA 07/03
–5–
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