ADF4355
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 4 ..................................................................................... 22
Register 5 ..................................................................................... 23
Register 6 ..................................................................................... 24
Register 7 ..................................................................................... 26
Register 8 ..................................................................................... 27
Register 9 ..................................................................................... 27
Register 10................................................................................... 28
Register 11................................................................................... 28
Register 12................................................................................... 29
Register Initialization Sequence ............................................... 29
Frequency Update Sequence..................................................... 29
RF Synthesizer—A Worked Example ...................................... 30
Reference Doubler and Reference Divider ............................. 30
Spurious Optimization and Fast Lock..................................... 30
Optimizing Jitter......................................................................... 31
Spur Mechanisms ....................................................................... 31
Lock Time.................................................................................... 31
Applications Information .............................................................. 32
Direct Conversion Modulator .................................................. 32
Power Supplies............................................................................ 33
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Circuit Description......................................................................... 12
Reference Input Section............................................................. 12
RF N Divider............................................................................... 12
Phase Frequency Detector (PFD) and Charge Pump............ 13
MUXOUT and Lock Detect...................................................... 13
Input Shift Registers................................................................... 13
Program Modes .......................................................................... 13
VCO.............................................................................................. 14
Output Stage................................................................................ 14
Register Maps.................................................................................. 16
Register 0 ..................................................................................... 18
Register 1 ..................................................................................... 19
Register 2 ..................................................................................... 20
Register 3 ..................................................................................... 21
Printed Circuit Board (PCB) Design Guidelines for a Chip-
Scale Package .............................................................................. 33
Output Matching........................................................................ 34
Outline Dimensions....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changes to Phase Resync Section ................................................ 21
Changes to Negative Bleed Section.............................................. 24
Change to Figure 36 ....................................................................... 24
Change to Reserved Section.......................................................... 25
Changes to Loss of Lock (LOL) Mode Section........................... 26
Changes to ADC Clock Divider (ADC_CLK_DIV) Section ... 28
Changes to Register Initialization Sequence Section and
Changes to Frequency Update Sequence Section ...................... 29
Changes to RF Synthesizer—A Worked Example Section........ 30
Change to Figure 44 ....................................................................... 32
Changes to Power Supplies Section and Figure 45 .................... 33
Changes to Frequency Update Sequence Section ...................... 29
Updated Outline Dimensions....................................................... 35
Changes to Ordering Guide .......................................................... 35
3/2016—Rev. 0 to Rev. A
Added Doubler Enabled Parameter, Table 1................................. 3
Changes to Table 2............................................................................ 5
Deleted VP, VVCO to AVDD Parameter, Table 3........................ 6
Changes to Table 4............................................................................ 7
Changes to Reference Input Section and INT, FRAC1, FRAC2,
MOD1, MOD2, and R Counter Relationship Section Title...... 12
Changes to Figure 28...................................................................... 16
Changes to Automatic Calibration (Autocalibration) Section
and Prescaler Section ..................................................................... 18
4/2015—Revision 0: Initial Version
Rev. B | Page 2 of 35
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