5秒后页面跳转
捷配首页

Datasheet > 信号电路 > 锁相环或频率合成电路> ADF4193BCPZ-RL7
ADF4193BCPZ-RL7 PDF预览

ADF4193BCPZ-RL7

更新时间： 2024-01-12 09:13:16
品牌 Logo 应用领域
亚德诺 - ADI 信号电路锁相环或频率合成电路信息通信管理
页数 文件大小 规格书
28页 595K
描述
Low Phase Noise, Fast Settling PLL Frequency Synthesizer

阅读下载

获取价格

ADF4193BCPZ-RL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC32,.2SQ,20针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.67
Is Samacsys：N模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm湿度敏感等级：3
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC32,.2SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：3 V认证状态：Not Qualified
座面最大高度：1 mm子类别：PLL or Frequency Synthesis Circuits
最大供电电流 (Isup)：27 mA最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：5 mmBase Number Matches：1

ADF4193BCPZ-RL7 数据手册

 浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第3页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第4页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第5页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第7页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第8页浏览型号ADF4193BCPZ-RL7的Datasheet PDF文件第9页 
ADF4193  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
24 V 2  
CMR  
1
2
P
PIN 1  
A
23  
22  
21  
R
A
D
OUT  
SET  
GND  
GND  
INDICATOR  
SW3  
3
4
2
3
A
1
GND  
ADF4193  
RF  
RF  
5
6
7
8
20 V 1  
IN–  
P
TOP VIEW  
19 LE  
18 DATA  
17 CLK  
IN+  
1
AV  
DD  
DV  
1
DD  
Figure 3. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No. Mnemonic Description  
1
CMR  
Common-Mode Reference Voltage for the Differential Amplifier’s Output Voltage Swing. Internally biased to  
three-fifths of VP3. Requires a 0.1 μF capacitor to ground.  
2
3
4
5
AOUT  
SW3  
Differential Amplifier Output to Tune the External VCO.  
Fast-Lock Switch 3. Closed while SW3 timeout counter is active.  
Analog Ground. This is the ground return pin for the differential amplifier and the RF section.  
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass  
capacitor, typically 100 pF.  
AGND1  
RFIN−  
6
7
RFIN+  
AVDD1  
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.  
Power Supply Pin for the RF Section. Nominally 3 V. A 100 pF decoupling capacitor to the ground plane should be  
placed as close as possible to this pin.  
8
DVDD1  
Power Supply Pin for the N Divider. Should be the same voltage as AVDD1. A 0.1 μF decoupling capacitor to ground  
should be placed as close as possible to this pin.  
9
DGND1  
Ground Return Pin for DVDD1.  
10  
DVDD2  
Power Supply Pin for the REFIN Buffer and R Divider. Nominally 3 V. A 0.1 μF decoupling capacitor to ground  
should be placed as close as possible to this pin.  
11  
REFIN  
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of  
100 kΩ (see Figure 15). This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.  
12  
13  
14  
15  
DGND  
2
Ground Return Pin for DVDD2 and DVDD3.  
Power Supply Pin for the Serial Interface Logic. Nominally 3 V.  
Ground Return Pin for the Σ-Δ Modulator.  
Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. A 0.1 μF decoupling capacitor to the ground plane  
should be placed as close as possible to this pin.  
DVDD3  
SDGND  
SDVDD  
16  
17  
18  
19  
20  
MUXOUT  
CLK  
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference  
frequency to be accessed externally (see Figure 35).  
Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high  
impedance CMOS input.  
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high  
impedance CMOS input.  
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is  
selected by the three LSBs.  
DATA  
LE  
VP1  
Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, should be at the same voltage at VP2.  
A 0.1 μF decoupling capacitor to ground should be placed as close as possible to this pin.  
21  
22  
DGND  
3
Ground Return Pin for VP1.  
Ground Return Pin for VP2.  
AGND2  
Rev. B | Page 6 of 28  
 
1...3456789...28

下载PDF

与ADF4193BCPZ-RL7相关器件

型号 品牌 描述 获取价格 数据表
ADF4196 ADI Low Phase Noise, Fast Settling, 6 GHz

获取价格
ADF4196BCPZ ADI Low Phase Noise, Fast Settling, 6 GHz

获取价格
ADF4196BCPZ-RL7 ADI Low Phase Noise, Fast Settling, 6 GHz

获取价格
ADF4206 ADI Dual RF PLL Frequency Synthesizers

获取价格
ADF4206BCHIPS ADI IC PLL FREQUENCY SYNTHESIZER, 500 MHz, UUC, DIE, PLL or Frequency Synthesis Circuit

获取价格
ADF4206BRU ADI Dual RF PLL Frequency Synthesizers

获取价格

与ADF4193BCPZ-RL7相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证