Datasheet > ADF4159WCCPZ

ADF4159WCCPZ

更新时间： 2022-02-26 12:01:16

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
36页	653K
描述
Direct Modulation/Fast Waveform Generating,

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ADF4159WCCPZ 数据手册

Data Sheet

ADF4159

Fast Lock Loop Filter Topology

FAST LOCK MODE

To use fast lock mode, an extra connection from the PLL to the

loop filter is needed. The damping resistor in the loop filter must

be reduced to ¼ of its value in wide bandwidth mode. This reduc-

tion is required because the charge pump current is increased

by 16 in wide bandwidth mode, and stability must be ensured.

The ADF4159 can operate in fast lock mode. In this mode, the

charge pump current is boosted and additional resistors are

connected to maintain the stability of the loop.

Fast Lock Timer and Register Sequences

When fast lock mode is enabled (Register R4, DB[20:19]), after

a write to Register R0, the PLL operates in a wide bandwidth

mode for a selected amount of time. Before fast lock is enabled,

the initialization sequence must be performed after the part is

first powered up (see the Initialization Sequence section). The

time in bandwidth mode is set by:

To further enhance stability and mitigate frequency overshoot

during a frequency change in wide bandwidth mode, Resistor R3

is connected (see Figure 53). During fast lock, the SW1 pin is

shorted to ground, and the SW2 pin is connected to CP (set

Bits DB[20:19] in Register R4 to 01 for fast lock divider).

The following two topologies can be used:

CLK₁× CLK₂/ f_PFD= Time in wide bandwidth

•

Divide the damping resistor (R1) into two values (R1 and

R1A) that have a ratio of 1:3 (see Figure 53).

Connect an extra resistor (R1A) directly from SW1 (see

Figure 54). The extra resistor must be selected such that the

parallel combination of an extra resistor and the damping

resistor (R1) is reduced to ¼ of the original value of R1.

where:

CLK₁= Register R2, DB[14:3].

CLK₂= Register R4, DB[18:7].

•

f_PFD= the PFD frequency.

Note that the fast lock feature does not work in ramp mode.

Fast Lock Example

For both topologies, the ratio R3:R2 must equal 1:4.

In this example, the PLL has f_PFDof 100 MHz and requires being

in wide bandwidth mode for 12 µs.

SW2

VCO

CLK₁× CLK₂/ f_PFD= 12 µs

CLK₁× CLK₂= (12 × 10⁻⁶)(100 × 10⁶) = 1200

ADF4159

SW1

Therefore, CLK1 = 12 and CLK2 = 100, which results in 12 µs.

R1A

Figure 53. Fast Lock Loop Filter Topology 1

SW2

VCO

ADF4159

R1A

SW1

Figure 54. Fast Lock Loop Filter Topology 2

For more fast lock topologies, see ADIsimPLL™.

Rev. E | Page 33 of 36

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