Datasheet > ADF4152HV

ADF4152HV

更新时间： 2022-02-26 12:01:16

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
27页	634K
描述
High Voltage, Fractional-N/Integer N PLL Synthesizer

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ADF4152HV 数据手册

ADF4152HV

Data Sheet

Parameter

POWER SUPPLIES

AV_DD

DV_DD, SDV_DD

V_P

Min

3.0

Typ

Max

3.±

Unit

Test Conditions/Comments

AV_DD

±.0

Set the V_Psupply at least 1 V above the

maximum desired tuning voltage

I_P

± to 24

2.5

±0

V_P= 30 V

I_DVDD+ I_SDVDD+ I_AVDD

Current per Output Divider

Each output divide by 2 consumes ± mA

typical

RF output stage is programmable

I_RFOUT

µA

Low Power Sleep Mode

RF OUTPUT CHARACTERISTICS

Output Frequency Using RF Output

Dividers

31.25

MHz

500 MHz VCO input and divide by 1± selected

Second-Order Harmonic Distortion

−19

−20

−13

−10

−4

dBc

dBm

Fundamental VCO output

Divided VCO output

Fundamental VCO output

Divided VCO output

Programmable in 3 dB steps

Pull-up supply on Pin 18 and Pin 19 varied

from 3.0 V to 3.± V

Third-Order Harmonic Distortion

Minimum RF Output Power(RF_OUT±)²

Maximum RF Output Power(RF_OUT±)²

Output Power Variation vs. Supply

±1

Output Power Variation vs. Temperature

Level of Signal with RF Mute Enabled

NOISE CHARACTERISTICS

±1

−37

dBm

From −40°C to +85°C

PDB_RFpin brought low; RF_OUT± = 2 GHz

Normalized In-Band Phase Noise Floor

−213

dBc/Hz

Low noise mode

(PN_SYNTH

)

−203

−113

−108

−155

−70

dBc/Hz

dBc

Low spur mode

Low noise mode

Low spur mode

Measured at 10 MHz offset

At RF_OUT+/RF_OUT− pins

Normalized 1/f Phase Noise (PN_{1_f})⁴

RF Output Divider Noise Floor

Spurious Signals Due to Phase

Frequency Detector (PFD) Frequency

−85

dBc

At VCO output

¹T_A= 25°C; AV_DD= DV_DD= 3.3 V; prescaler = 8/9; f_REFIN= 100 MHz; f_PFD= 25 MHz; f_RF= 1.75 GHz.

²Using 50 Ω resistors to AV_DD, into a 50 Ω load.

³This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

PN_SYNTH= PN_TOT− 10 log(f_PFD) − 20 log N

where PN_TOTis the measured in-band phase noise at the VCO output.

⁴The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The flicker noise is specified at a 10 kHz offset and normalized to 1 GHz. The

formula for calculating the 1/f noise contribution at an RF frequency (f_RF) and at a frequency offset (f) is given by PN = PN_{1_f}+ 10 log(10 kHz/f) + 20 log(f_RF/1 GHz). Both

the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

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