Datasheet > ADF4152HV

ADF4152HV

更新时间： 2022-02-26 12:01:16

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
27页	634K
描述
High Voltage, Fractional-N/Integer N PLL Synthesizer

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ADF4152HV 数据手册

Data Sheet

ADF4152HV

SPECIFICATIONS

AV_DD= DV_DD= SDV_DD= 3.3 V 10%; V_P= 6.0 V to 30 V; GND = 0 V; operating temperature range is T_A= −40°C to +85°C, unless

otherwise noted. V_CPis the voltage at the CP_OUTpin.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

REF_INCHARACTERISTICS

Input Frequency

300

MHz

For f < 10 MHz, ensure slew rate > 21 V/µs

Reference doubler enabled (DB25 bit in

Input Sensitivity

Input Capacitance

Input Current

0.7

AV_DD

5.0

±±0

V p-p

µA

Biased at AV_DD/2; ac coupling ensures AV_DD/2 bias

RF INPUT CHARACTERISTICS

For lower RF_IN± frequencies, ensure slew

rate > 400 V/µs

RF Input Frequency (RF_IN±)

RF Output Buffer Disabled

0.5

4.0

5.0

3.5

3.0

GHz

−10 dBm ≤ RF input power ≤ +5 dBm

−5 dBm ≤ RF input power ≤ +5 dBm

−10 dBm ≤ RF input power ≤ +5 dBm

RF Output Buffer Enabled

RF Output Buffer and Dividers

Enabled

Prescaler Output Frequency

PHASE DETECTOR

750

MHz

Phase Detector Frequency

2±

MHz

Low noise mode

Low spur mode

Integer N mode

HIGH VOLTAGE CHARGE PUMP

Charge Pump Current, I_CP

Sink/Source

High Value

Low Value

High Value vs. R_SET

384

µA

kΩ

R_SET= 5.1 kΩ

R_SET= 10 kΩ

R_SET= 3.3 kΩ

19±

3.3

594

R_SETRange

Sink and Source Current Matching

Absolute I_CPAccuracy

I_CPvs. V_CP

I_CPvs. Temperature

I_CPLeakage

2.5

1.0 V ≤ V_CP≤ (V_P− 1.0 V); V_P= ± V to 30 V

1.0 V ≤ V_CP≤ (V_P− 1.0 V)

V_CP= V_P/2

LOGIC INPUTS

Input Voltage

High, V_INH

2.0

Low, V_INL

0.±

Input Current, I_INH/I_INL

Input Capacitance, C_IN

LOGIC OUTPUTS

Output Voltage

High, V_OH

±1

15.0

µA

DV_DD− 0.4

CMOS output selected

I_OL= 500 µA

Low, V_OL

0.4

Output High Current, I_OH

500

µA

Rev. 0 | Page 3 of 27

1 234 5 6 7...27

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