ADF41513
Data Sheet
Parameter
LOGIC INPUTS
Input Voltage
High (VIH)
Min
Typ
Max
Unit
Test Conditions/Comments
1.4
V
The serial port interface (SPI) block can accept
both 1.8 V or 3.3 V logic inputs
Low (VIL)
Input Current (IINH, IINL
Input Capacitance (CIN)
LOGIC OUTPUTS
Output Voltage
High (VOH)
0.6
1
10
V
µA
pF
)
1.4
2.6
V
V
MUXOUT voltage = 1.8 V, DLD voltage = 1.8 V
MUXOUT voltage = 3.3 V, DLD voltage = 3.3 V
Low (VOL)
0.4
V
Output High Current, Output Low
Current (IOH, IOL)
500
µA
POWER SUPPLIES
AVDD1, AVDD2, AVDD3, AVDD4, AVDD5, VP 3.135
3.3
2
63.5
2.1
1.45
20
3.465
3.2
88
3.6
2
25
7
128.8
100
V
1
IDD1
IDD2
IDD3
IDD4
mA
mA
mA
mA
mA
mA
mA
µA
Current drawn by AVDD1
Current drawn by AVDD2
Current drawn by AVDD3
Current drawn by AVDD4
Current drawn by AVDD5
Current drawn by VP
Total current drawn by AVDDx and VP
TA = 25°C, CE is low, total of all rails
1
1
1
1
IDD5
IP
ITOTAL
6
95.1
Power-Down Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH
)
In Integer N Mode2
−235
dBc/Hz
PLL loop bandwidth (BW) = 1 MHz (Integer N
mode)
In Fractional-N Mode3
Normalized 1∕f Noise (PN1_f)3
SPURIOUS SIGNALS
−231
−128
dBc/Hz
dBc/Hz
PLL loop BW = 1 MHz (fractional-N mode)
10 kHz offset, normalized to 1 GHz
Reference Spurious
PFD Spurious
In-Band Integer Boundary
Spurious
−90
−87
−45
dBc
dBc
dBc
At reference = 100 MHz, PLL loop BW = 40 kHz
At PFD = 50 MHz, PLL loop BW = 40 kHz
10 kHz offset, PLL loop BW = 250 kHz
1 TA = 25°C, AVDDx = 3.3 V (where x = 1, 2, 3, or 4), prescaler (P) = 8/9, fRFIN = 26.5 GHz, REFIN = 124 MHz, PFD frequency input (fPFD) = 124 MHz.
2 The synthesizer phase noise floor is estimated by measuring the inband phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value)
and 10 log fPFD. PNSYNTH is the total phase noise measured at the VCO output (PNTOT) − 10 log fPFD − 20 log N.
3 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by phase noise (PN) = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are
modeled in the ADIsimPLL.
Rev. 0 | Page 4 of 30