ADF4107
Initialization Latch Method
Apply VDD
Program the initialization latch (11 in two LSBs of input word).
Make sure that the F1 bit is programmed to 0.
Note that there is an enable feature on the timer counter. It is
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1.
.
Charge Pump Currents
Next, do a function latch load (10 in two LSBs of the control
word), making sure that the F1 bit is programmed to a 0.
Then do an R load (00 in two LSBs).
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Figure 25.
Then do an AB load (01 in two LSBs).
When the Initialization Latch is loaded, the following occurs:
Prescaler Value
1. The function latch contents are loaded.
P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 300 MHz. Thus, with
an RF frequency of 4 GHz, a prescaler value of 16/17 is valid but
a value of 8/9 is not valid.
2. An internal pulse resets the R, AB, and timeout counters to
load-state conditions and also three-states the charge
pump. Note that the prescaler band gap reference and the
oscillator input buffer are unaffected by the internal reset
pulse, allowing close phase alignment when counting
resumes.
3. Latching the first AB counter data after the initialization
word will activate the same internal reset pulse. Successive
AB loads will not trigger the internal reset pulse unless
there is another initialization.
PD Polarity
This bit sets the phase detector polarity bit. See Figure 25.
CP Three-State
CE Pin Method
This bit controls the CP output pin. With the bit set high, the CP
output is put into three-state. With the bit set low, the CP output
is enabled.
Apply VDD
.
Bring CE low to put the device into power-down. This is an
asychronous power-down in that it happens immediately.
Program the function latch (10).
Program the R counter latch (00).
Program the AB counter latch (01).
Initialization Latch
The initialization latch is programmed when C2 and C1 are set
to 1 and 1. This is essentially the same as the function latch
(programmed when C2, C1 = 1, 0).
Bring CE high to take the device out of power-down. The R and
AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach steady state.
However, when the initialization latch is programmed an
additional internal reset pulse is applied to the R and AB
counters. This pulse ensures that the AB counter is at load point
when the AB counter data is latched and the device will begin
counting in close phase alignment.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after VDD was
initially applied.
If the latch is programmed for synchronous power-down (CE
pin is high; PD1 bit is high; PD2 bit is low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse
and so close phase alignment is maintained when counting
resumes.
Counter Reset Method
Apply VDD
.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
Do a Function Latch Load (10 in two LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
Do an R counter load (00 in two LSBs).
Do an AB counter load (01 in two LSBs).
Do a Function latch load (10 in two LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.
Device Programming after Initial Power-Up
After initially powering up the device, there are three ways to
program the device.
This sequence provides the same close alignment as the
initialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump, but does not trigger
synchronous power-down.
Rev. 0 | Page 17 of 20
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