Datasheet > 微控制器和处理器 > 时钟发生器> ADF4001BRUZ-R7

ADF4001BRUZ-R7

更新时间： 2024-02-21 18:31:09

品牌	Logo	应用领域
亚德诺 - ADI		晶体时钟发生器微控制器和处理器外围集成电路光电二极管信息通信管理
页数	文件大小	规格书
17页	860K
描述
200 MHz Clock Generator PLL

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

ADF4001BRUZ-R7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	5A991.B
HTS代码：	8542.39.00.01	风险等级：	0.97
Is Samacsys：	N	其他特性：	ALSO OPERATES AT 5 V NOMINAL SUPPLY
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	200 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	主时钟/晶体标称频率：	100 MHz
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压：	5.5 V	最小供电电压：	2.7 V
标称供电电压：	3 V	表面贴装：	YES
技术：	BICMOS	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

ADF4001BRUZ-R7 数据手册

ADF4001

PIN CONFIGURATIONS

SET

CPGND

AGND

MUXOUT

15 MUXOUT

14 LE

CPGND

AGND

ADF4001

TOP VIEW

(Not to Scale)

ADF4001

TOP VIEW

(Not to Scale)

DATA

CLK

13 DATA

12 CLK

11 CE

RF A 5

REF

DGND

NOTES

1. TRANSISTOR COUNT 6425 (CMOS)

AND 50 (BIPOLAR).

NOTES

1. TRANSISTOR COUNT 6425 (CMOS) AND 50 (BIPOLAR).

2. CONNECT EXPOSED PAD TO AGND.

LFCSP

TSSOP

Table 1. Pin Function Descriptions

TSSOP

Pin No.

LFCSP

Pin No.

Mnemonic Description

R_SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump

output current. The nominal voltage potential at the R_SETpin is 0.66 V. The relationship

between I_CPand R_SETis

23.5

R_SET

I_{CP MAX}



So, with R_SET= 4.7 kΩ, I_{CP MAX}= 5 mA.

Charge Pump Output. When enabled, this provides I_CPto the external loop filter which,

in turn, drives the external VCO or VCXO.

2, 3

CPGND

AGND

RF_INB

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path of the prescaler.

Complementary Input to the N counter. This point must be decoupled to the ground

plane with a small bypass capacitor, typically 100 pF. See Figure 3.

6, 7

RF_INA

AV_DD

Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.

Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the

analog ground plane should be placed as close as possible to this pin. AV_DDmust have the

same value as DV_DD

REF_IN

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and a dc

equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL

or CMOS crystal oscillator or can be ac-coupled.

9, 10

DGND

Digital Ground.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump

output into three-state mode. Taking the pin high will power up the device, depending on

the status of the power-down bit F2.

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The

data is latched into the 24-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control

bits. This input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is

loaded into one of the four latches, the latch being selected by using the control bits.

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.

Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the

digital ground plane should be placed as close as possible to this pin. DV_DDmust be the

MUXOUT

DV_DD

16, 17

same value as AV_DD

V_P

Charge Pump Power Supply. This should be greater than or equal to V_DD. In systems

where V_DDis 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning

range of up to 5 V.

N/A

EPAD

Exposed Pad. The exposed pad should be connected to AGND.

Rev. B | Page 4

1 2 345 6 7...17

下载PDF

与ADF4001BRUZ-R7相关器件

型号	品牌	描述	获取价格	数据表
ADF4001BRUZ-REEL	ADI	暂无描述	获取价格
ADF4001BRUZ-REEL7	ADI	IC 200 MHz, OTHER CLOCK GENERATOR, PDSO16, TSSOP-16, Clock Generator	获取价格
ADF4001BRUZ-RL	ADI	200 MHz Clock Generator PLL	获取价格
ADF4002	ADI	Phase Detector/Frequency Synthesizer	获取价格
ADF4002BCPZ	ADI	Phase Detector/Frequency Synthesizer	获取价格
ADF4002BCPZ-RL	ADI	Phase Detector/Frequency Synthesizer	获取价格

与ADF4001BRUZ-R7相关文章

STM32F030C6芯片介绍：主要参数分析、引脚配置说明、功耗及封装
2024-05-11

10
PCF8591数据手册解读：参数、引脚说明
2024-05-11

16
一文带你了解ss8050参数、引脚配置、应用指南
2024-05-11

7
深入解析AD7606高性能多通道模数转换器：资料手册参数分析
2024-05-10

9

产品中心

服务支持

精选活动

关于我们

帮助中心

ADF4001BRUZ-R7

ADF4001BRUZ-R7 技术参数

ADF4001BRUZ-R7 数据手册

与ADF4001BRUZ-R7相关器件

与ADF4001BRUZ-R7相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

ADF4001BRUZ-R7

ADF4001BRUZ-R7 技术参数

ADF4001BRUZ-R7 数据手册

与ADF4001BRUZ-R7相关器件

与ADF4001BRUZ-R7相关文章

您还可以找

您在本页遇到什么问题？