ADF4001–SPECIFICATIONS1
(AVDD = DVDD = 3 V ꢀ 10%, 5 V ꢀ 10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND =
CPGND = 0 V; RSET = 4.7 kꢁ; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 ꢁ.)
Parameter
B Version
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Frequency
RF Input Sensitivity
See Figure 3 for Input Circuit
5/165
–10/0
MHz min/max
dBm min/max
RF CHARACTERISTICS (5 V)
RF Input Frequency
10/200
20/200
MHz min/max
MHz min/max
–5/0 dBm min/max
–10/0 dBm min/max
REFIN CHARACTERISTICS
REFIN Input Frequency
See Figure 2 for Input Circuit
For f < 5 MHz, Use DC-Coupled Square Wave
5/104
–5
MHz min/max
dBm min
(0 to VDD
)
REFIN Input Sensitivity2
AC-Coupled. When DC-Coupled:
0 to VDD Max (CMOS Compatible)
REFIN Input Capacitance
REFIN Input Current
10
100
pF max
µA max
PHASE DETECTOR
Phase Detector Frequency3
55
MHz max
CHARGE PUMP
I
CP Sink/Source
High Value
Programmable: See Table V
With RSET = 4.7 kΩ
5
mA typ
µA typ
% typ
kΩ typ
nA typ
% typ
% typ
% typ
Low Value
Absolute Accuracy
625
2.5
2.7/10
1
2
1.5
2
With RSET = 4.7 kΩ
See Table V
RSET Range
I
CP Three-State Leakage Current
Sink and Source Current Matching
CP vs. VCP
0.5 V ≤ VCP ≤ VP – 0.5
0.5 V ≤ VCP ≤ VP – 0.5
VCP = VP/2
I
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
0.8 × DVDD
V min
VINL, Input Low Voltage
0.2 × DVDD
V max
µA max
pF max
I
INH/IINL, Input Current
1
10
CIN, Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
DVDD – 0.4
0.4
V min
V max
IOH = 500 µA
IOL = 500 µA
POWER SUPPLIES
AVDD
DVDD
VP
2.7/5.5
AVDD
AVDD/6.0
V min/V max
V min/V max
AVDD ≤ VP ≤ 6.0 V
IDD4 (AIDD + DIDD
)
ADF4001
IP
Low Power Sleep Mode
5.5
0.4
1
mA max
mA max
µA typ
4.5 mA typical
TA = 25°C
NOISE CHARACTERISTICS
ADF4001 Phase Noise Floor5
–161
–153
dBc/Hz typ
dBc/Hz typ
@ 200 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ VCXO Output
Phase Noise Performance6
200 MHz Output7
Spurious Signals
–99
dBc/Hz typ
@ 1 kHz Offset and 200 kHz PFD Frequency
200 MHz Output7
–90/–95
dBc typ/dBc typ
@ 200 kHz/400 kHz and 200 kHz PFD Frequency
NOTES
1Operating temperature range (B Version) is –40°C to +85°C.
2AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS compatible levels.
3Guaranteed by design. Sample tested to ensure compliance.
4TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz.
5The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
6The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.
7fREF = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 200 MHz; N = 1000; Loop B/W = 20 kHz.
IN
Specifications subject to change without notice.
–2–
B
REV.