ADE7169F16
Preliminary Technical Data
Mode 2 (9- bit UART with baud fixed at Fcore/64 or Fcore/32)
................................................................................................. 119
SPI Master Operating Modes.................................................. 126
SPI Interrupt and Status Flags ................................................ 127
I2C COMPATIBLE INTERFACE ............................................... 129
Serial Clock Generation .......................................................... 129
Slave addresses.......................................................................... 129
I2C SFR register list.................................................................. 129
Read and Write Operations .................................................... 130
I2C Receive and Transmit FIFOs........................................... 131
Dual Data Pointers ....................................................................... 132
I/O Ports ........................................................................................ 134
Parallel I/O ................................................................................ 134
Weak Internal Pullups Enabled.......................................... 134
Open Drain (Weak Internal Pullups Disabled) ............... 134
38 kHz Modulation.............................................................. 134
I/O SFR register list.................................................................. 135
Port 0.......................................................................................... 137
Port 1.......................................................................................... 138
Port 2.......................................................................................... 138
Outline Dimensions..................................................................... 139
Ordering Guide............................................................................. 140
Mode 3 (9-Bit UART with Variable Baud Rate)............... 120
UART Baud Rate Generation.................................................. 120
Mode 0 Baud Rate Generation ........................................... 120
Mode 2 Baud Rate Generation ........................................... 120
Modes 1 and 3 Baud Rate Generation............................... 120
Timer 1 Generated Baud Rates........................................... 120
Timer 2 Generated Baud Rates........................................... 120
UART Timer Generated Baud Rates.................................. 121
UART additional features........................................................ 122
Enhanced Error Checking................................................... 122
UART TxD signal modulation ........................................... 122
Serial Peripheral Interface Interface (SPI)................................. 123
SPI SFR register list .................................................................. 123
SPI pins ...................................................................................... 126
MISO (Master In, Slave Out Data I/O Pin) ...................... 126
MOSI (Master Out, Slave In Pin)....................................... 126
SCLK (Serial Clock I/O Pin)............................................... 126
(Slave Select Pin) ............................................................. 126
SS
Rev. PrD | Page 6 of 140