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ADDC02808PBTV/QMLH

更新时间： 2024-02-27 20:36:36

品牌	Logo	应用领域
亚德诺 - ADI		转换器模拟IC 信号电路脉冲局域网
页数	文件大小	规格书
20页	290K
描述
28 V, 200 W Pulsed DC/DC Converter with Integral EMI Filter

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ADDC02808PBTV/QMLH 技术参数

生命周期：	Obsolete	包装说明：	, FLANGE MT,2.8X1.8
Reach Compliance Code：	compliant	风险等级：	5.84
最大输入电压：	40 V	最小输入电压：	18 V
最大输出电流：	25 A	标称输出电压：	8 V
封装主体材料：	METAL	封装等效代码：	FLANGE MT,2.8X1.8
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
子类别：	Other Analog ICs	技术：	HYBRID
Base Number Matches：	1

ADDC02808PBTV/QMLH 数据手册

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ADDC02808PB

Table II. Output Response to a 24 A (1 A-25 A) Step in

Load Current (Compensation Optimized)

8.1

Typical

Deviation (Within 1%)

Settling Time See

7.9

7.8

7.7

7.6

C_LOAD

R_ESR

Figure

1,000 µF

2,000 µF

4,000 µF

10 mΩ

5 mΩ

2.5 mΩ

–4%

–2.5%

–1%

125 µs

100 µs

0 µs

Connection to Load

Pulse performance is dependent on minimizing the parasitic

impedances in the connection between the converter output and

the load and external capacitors. Low inductance and low resis-

tance connections should be used. Multilayer connections should

be avoided to minimize stray capacitance. The converter should

be placed as close to the load and external capacitors as possible.

7.5

7.4

–200 –100

100 200 300 400 500 600 700 800

TIME – ␮s

Figure 21. Predicted Response for 24 A Step Load

Change in Load Current, di/dt = 12 A/µs, for C_LOAD

2,000 µF and R_ESR= 5 mΩ

8.1

7.9

7.8

7.7

7.6

7.9

7.8

7.7

7.6

7.5

7.4

7.5

7.4

–200 –100

100 200 300 400 500 600 700 800

TIME – ␮s

Figure 23. Predicted Response for 24 A Step Load Change,

di/dt = 12 A/µs, with Factory Set Internal Compensation

Optimized for C_LOAD= 1,000 µF and R_ESR= 10 mΩ

–200 –100

100 200 300 400 500 600 700 800

TIME – ␮s

Figure 22. Predicted Response for 24 A Step Load

Change in Load Current, di/dt = 12 A/µs, for C_LOAD

4,000 µF and R_ESR= 2.5 mΩ

8.1

Factory Set Internal Compensation

If the user knows the external load capacitance and R_ESRto be

used in the application and if the application requires better

pulse response than is summarized in Table I, then the internal

feedback compensation can be modified at the factory to im-

prove the transient response. In these instances, the compensa-

tion is optimized for a particular C_LOADat the expense of

performing well over a broader range of C_LOAD. The predicted

maximum output voltage deviation and settling times for fac-

tory-modified feedback compensation are shown in Figures 23,

24, and 25, and summarized in Table II, for three combinations

of C_LOADand R_ESR. As can be seen, optimizing the compensa-

tion for a given load capacitance gives the best transient re-

sponse in terms of both voltage deviation and settling time.

7.9

7.8

7.7

7.6

7.5

7.4

–200 –100

100 200 300 400 500 600 700 800

TIME – ␮s

Figure 24. Predicted Response for 24 A Step Load Change,

di/dt = 12 A/µs, with Factory Set Internal Compensation

Optimized for C_LOAD= 2,000 µF and R_ESR= 5 mΩ

REV. A

–9–

1...6 7 8910 11 12...20

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与ADDC02808PBTV/QMLH相关器件

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