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ADDC02808PBTV/QMLH

更新时间： 2024-02-08 17:33:23

品牌	Logo	应用领域
亚德诺 - ADI		转换器模拟IC 信号电路脉冲局域网
页数	文件大小	规格书
20页	290K
描述
28 V, 200 W Pulsed DC/DC Converter with Integral EMI Filter

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ADDC02808PBTV/QMLH 技术参数

生命周期：	Obsolete	包装说明：	, FLANGE MT,2.8X1.8
Reach Compliance Code：	compliant	风险等级：	5.84
最大输入电压：	40 V	最小输入电压：	18 V
最大输出电流：	25 A	标称输出电压：	8 V
封装主体材料：	METAL	封装等效代码：	FLANGE MT,2.8X1.8
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
子类别：	Other Analog ICs	技术：	HYBRID
Base Number Matches：	1

ADDC02808PBTV/QMLH 数据手册

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ADDC02808PB

250

8.1

MAXIMUM PEAK

POWER LIMIT

200

7.9

7.8

7.7

7.6

10W ave

100W ave

150

12A STEP CHANGE

24A STEP CHANGE

50W ave

100

MAXIMUM CONTINUOUS

POWER LIMIT

7.5

7.4

100

125

150

–200 –100

100 200 300 400 500 600 700 800

PULSEWIDTH – ms

TIME – ␮s

Figure 17. Largest On-State Power vs. Pulsewidth that

Maintains T_JMAX≤ 110°C at 90°C Baseplate

Figure 19. Predicted Response to 12 A and 24 A Step

Change in Load Current, di/dt = 12 A/µs, for C_LOAD

1000 µF and R_ESR= 10 mΩ

TRANSIENT RESPONSE

The standard ADDC02808PB is designed to deliver large

changes, or pulses, in load current with minimum output volt-

age deviation and an ultrafast return to the nominal output

voltage. The compensation of the feedback loop is optimized,

and output stability is insured, for a broad range of external load

capacitance extending from 500 µF (R_ESR= 20 mΩ) to 4,000 µF

(R_ESR= 2.5 mΩ). The variables that impact pulse performance

(the maximum output voltage deviation and the settling time)

are:

1. Size of step change in the output current.

2. Amount of external load capacitance.

3. Internal compensation of the feedback loop (factory set).

4. Connection from converter output to load.

Step Change

If the step change is less than 24 A, the pulse response will

improve. For instance, with a 12 A step change, Figure 19

shows a comparison of the response for a 24 A step change and

a 12 A step change in load.

Load Capacitance

Varying the external load capacitance and associated R_ESRbe-

tween the range of C_LOAD= 500 µF (R_ESR= 20 mΩ) and C_LOAD

= 4,000 µF (R_ESR= 2.5 mΩ) results in the predicted waveforms

shown in Figures 20, 21, and 22. As can be seen, the larger the

capacitor, the smaller the deviation, but the longer the settling

time. Table I lists the maximum output voltage deviations and

settling times for the four combinations of C_LOADand R_ESR

mentioned above. Note that these are based on the standard

compensation for the feedback loop.

Extensive modeling of the converter with ADI proprietary soft-

ware permits analysis and prediction of the impact each of these

parameters has on the pulse response. The analyses in this data

sheet are based on the load capacitance being comprised of

100 µF, 100 mΩ tantalum load capacitors such as the CSR21

style. Figure 18 is the prediction of the standard converter’s

response to a 24 A step change in load current (from 1 A to

25 A) with a load capacitance of 1,000 µF (R_ESR= 10 mΩ).

This is very close to the measured pulse response under the

same conditions shown in Figure 6.

Table I. Output Response to a 24 A (1 A–25 A) Step in Load

Current (Standard Compensation)

Typical

Deviation (Within 1%)

Settling Time See

C_LOAD

R_ESR

Figure

500 µF

20 mΩ

10 mΩ

5 mΩ

–7%

–6%

–5%

–4%

150 µs

175 µs

200 µs

250 µs

1,000 µF

2,000 µF

4,000 µF

2.5 mΩ

8.1

7.9

7.8

7.7

7.6

7.9

7.8

7.7

7.6

7.5

7.4

7.5

7.4

–200 –100

100 200 300 400 500 600 700 800

–200 –100

100 200 300 400 500 600 700 800

TIME – ␮s

Figure 18. Predicted Response to 24 A Step Change in

Load Current, di/dt = 12 A/µs, for C_LOAD= 1,000 µF and

Figure 20. Predicted Response for 24 A Step Load

Change in Load Current, di/dt = 12 A/µs, for C_LOAD

= 500 µF and R_ESR= 20 mΩ

R_ESR= 10 mΩ

–8–

REV. A

1...5 6 789 10 11...20

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