ADCMP602XRMZ

更新时间： 2024-01-04 09:37:23

品牌	Logo	应用领域
亚德诺 - ADI		比较器
页数	文件大小	规格书
16页	275K
描述
IC COMPARATOR, 5000 uV OFFSET-MAX, 3 ns RESPONSE TIME, PDSO8, MSOP-8, Comparator

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ADCMP602XRMZ 技术参数

生命周期：	Obsolete	零件包装代码：	MSOP
包装说明：	TSSOP,	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.77
Is Samacsys：	N	放大器类型：	COMPARATOR
最大平均偏置电流 (IIB)：	5 µA	最大输入失调电压：	5000 µV
JESD-30 代码：	S-PDSO-G8	JESD-609代码：	e3
长度：	3 mm	功能数量：	1
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-40 °C	输出类型：	PUSH-PULL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	SQUARE	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：	Not Qualified	标称响应时间：	3 ns
座面最大高度：	1.1 mm	子类别：	Comparator
供电电压上限：	6 V	表面贴装：	YES
温度等级：	AUTOMOTIVE	端子面层：	TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	3 mm
Base Number Matches：	1

ADCMP602XRMZ 数据手册

ADCMP600/ADCMP601/ADCMP602

TIMING INFORMATION

Figure 2 illustrates the ADCMP600/ADCMP601/ADCMP602 latch timing relationships. Table 2 provides definitions of the terms shown

in Figure 2.

1.1V

LATCH ENABLE

t_S

t_PL

t_H

DIFFERENTIAL

INPUT VOLTAGE

± V

t_PDL

t_PLOH

Q OUTPUT

50%

t_F

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing

Description

t_PDH

t_PDL

t_PLOH

t_PLOL

t_H

Input to output high delay

Propagation delay measured from the time the input signal crosses the reference ( the

input offset voltage) to the 50% point of an output low-to-high transition.

Propagation delay measured from the time the input signal crosses the reference ( the

input offset voltage) to the 50% point of an output high-to-low transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output low-to-high transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output high-to-low transition.

Input to output low delay

Latch enable to output high delay

Latch enable to output low delay

Minimum hold time

Minimum time after the negative transition of the latch enable signal that the input signal

must remain unchanged to be acquired and held at the outputs.

t_PL

t_S

Minimum latch enable pulse width

Minimum setup time

Minimum time that the latch enable signal must be high to acquire an input signal change.

Minimum time before the negative transition of the latch enable signal occurs that an

input signal change must be present to be acquired and held at the outputs.

t_R

Output rise time

Output fall time

Voltage overdrive

Amount of time required to transition from a low to a high output as measured at the 20%

and 80% points.

Amount of time required to transition from a high to a low output as measured at the 20%

and 80% points.

t_F

V_OD

Difference between the input voltages V_Aand V_B.

Rev. 0 | Page 5 of 16

1 2 3 456 7 8...16

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