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ADCMP573JCP

更新时间： 2024-02-26 08:52:53
品牌 Logo 应用领域
亚德诺 - ADI 比较器
页数 文件大小 规格书
16页 544K
描述
IC COMPARATOR, 5000 uV OFFSET-MAX, QCC16, MO-220-VEED-2, LFCSP-16, Comparator

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ADCMP573JCP 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFN
包装说明：MO-220-VEED-2, LFCSP-16针数：16
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
放大器类型：COMPARATOR最大平均偏置电流 (IIB)：50 µA
最大输入失调电压：5000 µVJESD-30 代码：S-XQCC-N16
JESD-609代码：e0长度：3 mm
湿度敏感等级：3功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC16,.12SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3/5 V
认证状态：Not Qualified座面最大高度：1 mm
子类别：Comparator最大压摆率：76 mA
供电电压上限：6 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BIPOLAR
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15) - with Silver (Ag) barrier
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mmBase Number Matches：1

ADCMP573JCP 数据手册

 浏览型号ADCMP573JCP的Datasheet PDF文件第3页浏览型号ADCMP573JCP的Datasheet PDF文件第4页浏览型号ADCMP573JCP的Datasheet PDF文件第5页浏览型号ADCMP573JCP的Datasheet PDF文件第7页浏览型号ADCMP573JCP的Datasheet PDF文件第8页浏览型号ADCMP573JCP的Datasheet PDF文件第9页 
ADCMP572/ADCMP573  
Preliminary Technical Data  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
16  
15  
14  
13  
PIN1  
1
2
3
4
12  
V
CCO  
V
TP  
ADCMP572  
ADCMP573  
TOP VIEW  
(Not to Scale)  
V
V
11  
10  
9
Q
Q
P
N
V
V
CCO  
TN  
5
6
7
8
Figure 2. ADCMP572/ADCMP573 Pin Configuration  
Table 3. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
2
VTP  
VP  
Termination Resistor Return Pin for VP Input.  
Noninverting Analog Input.  
3
VN  
Inverting Analog Input.  
4
5, 16  
6
VTN  
VCCI  
LE  
Termination Resistor Return Pin for VN Input.  
Positive Supply Voltage for Input Stage.  
Latch Enable Input Pin, Inverting Side.  
In compare mode (LE = low), the output tracks changes at the input of the comparator.  
In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being  
placed in latch mode. LE must be driven in compliment with LE.  
7
8
LE  
Latch Enable Input Pin, Noninverting Side.  
In compare mode (LE = high), the output tracks changes at the input of the comparator.  
In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being  
placed in latch mode. LE must be driven in compliment with LE.  
VCCO/VTT  
Termination Return Pin for the LE/LE Input Pins.  
For the ADCMP572 (CML output stage), this pin should be connected to the positive VCCO supply.  
For the ADCMP573 (RSPECL output stage), this pin should be connected to the VCCO – 2 V  
termination potential.  
13, 15  
9, 12  
10  
GND  
VCCO  
Q
Ground.  
Positive Supply Voltage for the CML/RSPECL Output Stage.  
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than  
the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the  
LE/LE description (Pins 6 and 7) for more information.  
11  
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater  
than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See  
the LE/LE description (Pins 6 and 7) for more information.  
14  
HYS  
N/C  
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a  
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of  
RHYS hysteresis control resistor.  
The metallic back surface of the package is not electrically connected to any part of the circuit, and it  
can be left floating for best electrical isolation between the package handle and the substrate of the  
die. But it can also be soldered to the application board if improved thermal and/or mechanical  
stability is desired.  
Heatsink  
Rev. PrB | Page 6 of 16  
 
1...3456789...16

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