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ADCLK905_15 PDF预览

ADCLK905_15

更新时间: 2022-02-26 11:56:12
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 1104K
描述
Ultrafast SiGe ECL Clock/Data Buffers

ADCLK905_15 数据手册

 浏览型号ADCLK905_15的Datasheet PDF文件第5页浏览型号ADCLK905_15的Datasheet PDF文件第6页浏览型号ADCLK905_15的Datasheet PDF文件第7页浏览型号ADCLK905_15的Datasheet PDF文件第9页浏览型号ADCLK905_15的Datasheet PDF文件第10页浏览型号ADCLK905_15的Datasheet PDF文件第11页 
ADCLK905/ADCLK907/ADCLK925  
TYPICAL PERFORMANCE CHARACTERISTICS  
VCC = 3.3 V, VEE = 0.0 V, TA = 25°C, outputs terminated 50 Ω to VCC − 2 V, unless otherwise noted.  
2.37V  
2.37V  
Q
Q
Q
Q
1.37V  
1.37V  
200ps/DIV  
100ps/DIV  
Figure 7. Output Waveform, VCC = 3.3 V  
Figure 10. Output Waveform, VCC = 3.3 V  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
AGILENT E5500  
AGILENT E5500  
CARRIER: 122.88MHz  
NO SPURS  
CARRIER: 622.08MHz  
NO SPURS  
10  
100  
1k  
10k  
100k  
f (Hz)  
1M  
10M  
100M  
10  
100  
1k  
10k  
100k  
f (Hz)  
1M  
10M  
100M  
Figure 8. Phase Noise at 122.88 MHz  
Figure 11. Phase Noise at 622.08 MHz  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
300  
250  
200  
150  
100  
50  
AGILENT E5500  
CARRIER: 245.76MHz  
NO SPURS  
0
10  
100  
1k  
10k  
100k  
f (Hz)  
1M  
10M  
100M  
0
1
2
3
4
5
6
7
8
INPUT SLEW RATE (V/ns)  
Figure 9. Phase Noise at 245.76 MHz  
Figure 12. RMS Jitter vs. Input Slew Rate  
Rev. 0 | Page 8 of 16  
 

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