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ADCDS-1410LP-C PDF预览

ADCDS-1410LP-C

更新时间: 2024-02-26 11:06:13
品牌 Logo 应用领域
村田 - MURATA 光电二极管商用集成电路
页数 文件大小 规格书
14页 436K
描述
D/A Converter, 14-Bit, 1 Channel, CDIP40

ADCDS-1410LP-C 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:DIP, DIP40,.9Reach Compliance Code:compliant
风险等级:5.59转换器类型:D/A CONVERTER
JESD-30 代码:R-XDIP-T40模拟输入通道数量:1
位数:14端子数量:40
最高工作温度:70 °C最低工作温度:
封装主体材料:CERAMIC封装代码:DIP
封装等效代码:DIP40,.9封装形状:RECTANGULAR
封装形式:IN-LINE电源:+-5,12 V
认证状态:Not Qualified子类别:Other Converters
表面贴装:NO温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

ADCDS-1410LP-C 数据手册

 浏览型号ADCDS-1410LP-C的Datasheet PDF文件第2页浏览型号ADCDS-1410LP-C的Datasheet PDF文件第3页浏览型号ADCDS-1410LP-C的Datasheet PDF文件第4页浏览型号ADCDS-1410LP-C的Datasheet PDF文件第6页浏览型号ADCDS-1410LP-C的Datasheet PDF文件第7页浏览型号ADCDS-1410LP-C的Datasheet PDF文件第8页 
®
®
ADCDS-1410  
14-Bit, 10 Megapixels/Second CCD Image Converter  
Offset Adjustment  
For Example:  
Manual offset adjustment for the ADCDS-1410 can be accomplished  
using the adjustment circuit shown in Figure 3. A software controlled  
D/A converter can be substituted for the 20KΩ potentiometer. The offset  
adjustment feature allows the user to adjust the Offset/Dark Current level  
of the ADCDS-1410 until the output bits are 00 0000 0000 0000 and the  
LSB flickers between 0 and 1. Offset adjust should be performed before  
gain adjust to avoid interaction. The ADCDS-1410's offset adjustment is  
dependent on the value of the external series resistor used in the offset  
adjust circuit (Figure 3). The Offset Adjustment graph (Figure ꢀ) illustrates  
the typical relationship between the external series resistor value and its  
offset adjustment capability utilizing 5V supplies.  
External 50KΩ resistor:  
1. 10mV of noise or voltage variation at the potentiometer  
will produce 0.25LSB's of output variation.  
2. 100mV of noise or voltage variation at the potentiometer  
will produce 2.5LSB's of output variation.  
The Offset Adjustment Sensitivity graph (Figure 7) illustrates the offset  
adjustment sensitivity over a wide range of external resistor and noise  
values. If a large offset voltage is required, it is recommended that a very  
low noise external reference be used in the offset adjust circuit in place  
of power supplies. The ADCDS-1410's +2.4V reference output could be  
configured to provide the reference voltage for this type of application.  
Fine Gain Adjustment  
OFFSET ADJUSTMENT SENSITIVITY  
Fine gain adjustment is provided to compensate for the tolerance of the  
external coarse gain resistor (Rext) and/or the unavailability of exact  
coarse gain resistor (Rext) values. Note, the fine gain adjustment will not  
change the expected input amplifier's full scale VOUT (2.8Vp-p.) Instead,  
the gain of the ADCDS-1410's internal A/D is adjusted allowing the actual  
input amplifier's full scale VOUT to produce an output code of all ones (11  
1111 1111 1111).  
It should be noted that with increasing amounts of offset adjustment  
(smaller values of external series resistors), the ADCDS-1410 becomes  
more susceptible to power supply noise or voltage variations seen at the  
wiper of the offset potentiometer.  
ADCDS-1410  
DAC  
Fine gain adjustment for the ADCDS-1410 is accomplished using the  
adjustment circuit shown below (Figure 5). A software controlled D/A  
converter can be substituted for the 20KΩ potentiometer. The fine gain  
adjust circuit ensures that the video input signal (saturated signal) will be  
properly scaled to obtain the desired Full Scale digital output of 11 1111  
1111 1111, with the LSB flickering between 0 and 1. Fine gain adjust  
should be performed following the offset adjust to avoid interaction. The  
fine gain adjust provides 25ꢀ codes of adjust when 5V supplies are  
used for the Fine Gain Adjust Circuit.  
or  
Fine  
Gain  
Adjust  
1
+5V  
100  
Ω
20K  
–5V  
Figure 5. Fine Gain Adjustment Circuit  
Offset Adjustment Sensitivity  
External Series Resistor vs. Output Variation (LSB's)  
Offset Adjustment vs. External Series Resistor  
10000  
1000  
100  
100  
Peak-Peak  
variation at  
potentiometer  
10  
1
100mV  
10mV  
1mV  
0.1  
0.01  
10  
0
5K 10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K  
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k  
External Series Resistor (Ohm's)  
External Series Resistor Value (Ohms)  
Figure 6. Offset Adjustment vs. External Series Resistor  
Figure 7. Offset Adjustment Sensitivity  
DATEL  
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA  
Tel: (508) 339-3000  
www.datel.com  
e-mail: help@datel.com  
31 Mar 2011 MDA_ADCDS-1410.B04 Page 5 of 14  

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