Datasheet > ADC614JH

ADC614JH

更新时间： 2024-02-29 22:30:22

品牌	Logo	应用领域
BB		转换器
页数	文件大小	规格书
15页	197K
描述
ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid, CDIP46, CERAMIC, DIP-46

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技术参数
数据手册

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ADC614JH 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	CERAMIC, DIP-46	Reach Compliance Code：	unknown
风险等级：	5.89	最大模拟输入电压：	1.25 V
最小模拟输入电压：	-1.25 V	转换器类型：	ADC, FLASH METHOD
JESD-30 代码：	R-CDIP-T46	JESD-609代码：	e0
最大线性误差 (EL)：	0.012%	标称负供电电压：	-15 V
模拟输入通道数量：	1	位数：	14
功能数量：	1	端子数量：	46
最高工作温度：	85 °C	最低工作温度：
输出位码：	2'S COMPLEMENT BINARY, COMPLEMENTARY 2'S COMPLEMENT	输出格式：	PARALLEL, WORD
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	DIP
封装等效代码：	DIP46,1.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5,-5.2,+-15 V	认证状态：	Not Qualified
采样速率：	5.12 MHz	采样并保持/跟踪并保持：	SAMPLE
子类别：	Analog to Digital Converters	标称供电电压：	15 V
表面贴装：	NO	技术：	HYBRID
温度等级：	OTHER	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

ADC614JH 数据手册

HIGH, then output data “N-3” will be valid on the rising

edge of Convert Command “N”. These timing relationships

are valid at any conversion rate up to 5.12MHz, the data

setup time before the rising Convert Command edge is about

50ns.

Data should be latched into external TTL latches that can

operate reliably with a set-up time of 6ns minimum. Two

74F574 hex latches are recommended.

DATA OUTPUT

(2) Data Valid timing option (pin 29 = LOW)—With this

option, data from conversion “N” becomes valid after a

fixed delay from the rising edge of Convert Command “N”.

The delay is about 165ns . At about t = 185ns, the Data Valid

strobe signal will rise. This strobe signal may be connected

directly to the clock input of the external data latches,

providing a data setup time of approximately 20ns.

Output logic inversion can be accomplished by programming

pin 27. Binary Two’s Complement or Inverted Binary Two's

Complement output data format is available (Table II).

The ADC614 output logic is TTL compatible. The 3-state

output is controlled by ENABLE pin 25. For normal opera-

tion pin 25 will be tied LO. A logic HI on pin 25 will switch

the output data register to a high-impedance state (Figure

14). Output OFF leakage current I_OZLand I_OZHwill be less

than 50µA over the converter's specified operating tempera-

ture range. The 3-state output should be isolated from noisy

digital bus lines as the noise can couple back through the

OFF data register and create noise in the ADC.

See Figure 13 for timing relationships. Pin 28 must be left

HIGH at all times when using the Data Valid timing option.

This method does not require subsequent conversions in

order to read the data (i.e., single-shot conversion capabil-

ity). Therefore, the Data Valid option is useful in systems

where the very first data latch output after power-up must

represent a valid conversion.

DIGITAL INPUTS

Logic inputs are TTL compatible. Open inputs will assume

a HI logic state; unused inputs may be allowed to float or

they may be tied to an appropriate TTL logic level.

DATA LATCHED BY

CONVERT COMMAND

DATA LATCHED BY

DATA VALID STROBE

PIN NUMBER

N-2

N-1

OFFSET AND GAIN ADJUSTMENT

The ADC614 is carefully laser-trimmed to achieve its rated

accuracy without external adjustments. If desired, both gain

error and input offset voltage error may be trimmed with

external potentiometers (Figure 15). Trim range is typically

only 0.1%; large offsets and gain changes should be made

TABLE I. Pipeline Delay Selection Logic.

DIGITAL DATA OUTPUT LOGIC CODING

BINARY TWO'S INVERTED BINARY

COMPLEMENT (BTC) TWO'S COMPLEMENT

INPUT VOLTAGE

(EXACT CENTER OF CODE)

PIN 27 = LO

(BTC) PIN 27 = HI

+FS (+1.25V)

01111111111111⁽¹⁾

01111111111111

01111111111110

01100000000000

01000000000000

00100000000000

00000000000001

00000000000000

11111111111111

11100000000000

11000000000000

10100000000000

10000000000001

10000000000000

10000000000000⁽¹⁾

10000000000000

10000000000001

10011111111111

10111111111111

11011111111111

11111111111110

11111111111111

00000000000000

00011111111111

00111111111111

01011111111111

01111111111110

01111111111111

+FS –1LSB (+1.24985V)

+FS –2LSB (+1.24969V)

+3/4 FS (+0.9375V)

+1/2 FS (+0.6250V)

+1/4 FS (+0.3125V)

+1LSB (+152µV)

Insulated

ADC614

BNC

Signal

Input

Signal

Input

Bipolar Zero (0V)

–1LSB (–152µV)

–1/4 FS (–0.3125V)

–1/2 FS (–0.625V)

–3/4 FS (–0.9375V)

–FS + 1LSB (–1.24985V)

–FS (–1.25V)

Analog

Common

Balun

Transformer

MSB

NOTE: (1) Indicates overrange condition.

LSB

MSB

LSB

= Cable Termination Impedance

FIGURE 6. Floating-Input Balun Transformer.

TABLE II. Coding Table for 14-bit ±1.25V ADC Function.

Amidon FT 50-43

Ferrite Core

Impedance = 1:1

#26 AWG Bifilar Wound

FIGURE 7. Common-Mode Choke Transformer Windings.

ADC614

1...8 9 101112 13 14 15

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与ADC614JH相关器件

型号	品牌	描述	获取价格	数据表
ADC614JHQ	BB	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid,	获取价格
ADC614KH	BB	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid, CDIP46, CERAM	获取价格
ADC614KHQ	BB	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid,	获取价格
ADC614LH	BB	ADC, Flash Method, 14-Bit, 1 Func, Parallel, Word Access, Hybrid,	获取价格
ADC614LHQ	BB	ADC, Flash Method, 14-Bit, 1 Func, 1 Channel, Parallel, Word Access, Hybrid,	获取价格
ADC-6-1R	MINI	Directional Coupler 50Ω 5 to 200 MHz	获取价格

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