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ADC1206S055H/C1,55 PDF预览

ADC1206S055H/C1,55

更新时间: 2024-11-19 15:27:39
品牌 Logo 应用领域
恩智浦 - NXP 信息通信管理转换器
页数 文件大小 规格书
32页 504K
描述
1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP44, 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44

ADC1206S055H/C1,55 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44针数:44
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.68最大模拟输入电压:2 V
最小模拟输入电压:1 V转换器类型:ADC, PROPRIETARY METHOD
JESD-30 代码:S-PQFP-G44JESD-609代码:e3
长度:10 mm最大线性误差 (EL):0.1099%
湿度敏感等级:3模拟输入通道数量:1
位数:12功能数量:1
端子数量:44最高工作温度:85 °C
最低工作温度:-40 °C输出位码:BINARY, 2'S COMPLEMENT BINARY
输出格式:PARALLEL, WORD封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP44,.47SQ,32
封装形状:SQUARE封装形式:FLATPACK
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified采样速率:55 MHz
采样并保持/跟踪并保持:SAMPLE座面最大高度:2.1 mm
子类别:Analog to Digital Converters标称供电电压:5 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:TIN
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:10 mmBase Number Matches:1

ADC1206S055H/C1,55 数据手册

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ADC1206S040/055/070  
Single 12 bits ADC, up to 40 MHz, 55 MHz or 70 MHz  
Rev. 02 — 12 August 2008  
Product data sheet  
1. General description  
The ADC1206S040/055/070 are a family of BiCMOS 12-bit Analog-to-Digital Converters  
(ADC) optimized for a wide range of applications such as cellular infrastructures,  
professional telecommunications, imaging, and digital radio. It converts the analog input  
signal into 12-bit binary coded digital words at a maximum sampling rate of 70 MHz. All  
static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL) and CMOS  
compatible and all outputs are CMOS compatible. A sine wave clock input signal can also  
be used.  
2. Features  
I 12-bit resolution  
I Sampling rate up to 70 MHz  
I 3 dB bandwidth of 245 MHz  
I 5 V power supplies and 3.3 V output power supply  
I Binary or twos complement CMOS outputs  
I In-range CMOS compatible output  
I TTL and CMOS compatible static digital inputs  
I TTL and CMOS compatible digital outputs  
I Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible  
I Power dissipation 550 mW (typical)  
I Low analog input capacitance (typical 2 pF), no buffer amplifier required  
I Integrated sample and hold amplifier  
I Differential analog input  
I External amplitude range control  
I Voltage controlled regulator included  
I 40 °C to +85 °C ambient temperature  
3. Applications  
High-speed analog-to-digital conversion for:  
I Cellular infrastructure  
I Professional telecommunication  
I Digital radio  
I Radar  
I Medical imaging  
I Fixed network  
I Cable modem  
 
 
 

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